pl08x.h 4.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
  4. *
  5. * Copyright (C) 2005 ARM Ltd
  6. * Copyright (C) 2010 ST-Ericsson SA
  7. *
  8. * pl08x information required by platform code
  9. *
  10. * Please credit ARM.com
  11. * Documentation: ARM DDI 0196D
  12. */
  13. #ifndef AMBA_PL08X_H
  14. #define AMBA_PL08X_H
  15. /* We need sizes of structs from this header */
  16. #include <linux/dmaengine.h>
  17. #include <linux/interrupt.h>
  18. struct pl08x_driver_data;
  19. struct pl08x_phy_chan;
  20. struct pl08x_txd;
  21. /* Bitmasks for selecting AHB ports for DMA transfers */
  22. enum {
  23. PL08X_AHB1 = (1 << 0),
  24. PL08X_AHB2 = (1 << 1)
  25. };
  26. /**
  27. * struct pl08x_channel_data - data structure to pass info between
  28. * platform and PL08x driver regarding channel configuration
  29. * @bus_id: name of this device channel, not just a device name since
  30. * devices may have more than one channel e.g. "foo_tx"
  31. * @min_signal: the minimum DMA signal number to be muxed in for this
  32. * channel (for platforms supporting muxed signals). If you have
  33. * static assignments, make sure this is set to the assigned signal
  34. * number, PL08x have 16 possible signals in number 0 thru 15 so
  35. * when these are not enough they often get muxed (in hardware)
  36. * disabling simultaneous use of the same channel for two devices.
  37. * @max_signal: the maximum DMA signal number to be muxed in for
  38. * the channel. Set to the same as min_signal for
  39. * devices with static assignments
  40. * @muxval: a number usually used to poke into some mux regiser to
  41. * mux in the signal to this channel
  42. * @addr: source/target address in physical memory for this DMA channel,
  43. * can be the address of a FIFO register for burst requests for example.
  44. * This can be left undefined if the PrimeCell API is used for configuring
  45. * this.
  46. * @single: the device connected to this channel will request single DMA
  47. * transfers, not bursts. (Bursts are default.)
  48. * @periph_buses: the device connected to this channel is accessible via
  49. * these buses (use PL08X_AHB1 | PL08X_AHB2).
  50. */
  51. struct pl08x_channel_data {
  52. const char *bus_id;
  53. int min_signal;
  54. int max_signal;
  55. u32 muxval;
  56. dma_addr_t addr;
  57. bool single;
  58. u8 periph_buses;
  59. };
  60. enum pl08x_burst_size {
  61. PL08X_BURST_SZ_1,
  62. PL08X_BURST_SZ_4,
  63. PL08X_BURST_SZ_8,
  64. PL08X_BURST_SZ_16,
  65. PL08X_BURST_SZ_32,
  66. PL08X_BURST_SZ_64,
  67. PL08X_BURST_SZ_128,
  68. PL08X_BURST_SZ_256,
  69. };
  70. enum pl08x_bus_width {
  71. PL08X_BUS_WIDTH_8_BITS,
  72. PL08X_BUS_WIDTH_16_BITS,
  73. PL08X_BUS_WIDTH_32_BITS,
  74. };
  75. /**
  76. * struct pl08x_platform_data - the platform configuration for the PL08x
  77. * PrimeCells.
  78. * @slave_channels: the channels defined for the different devices on the
  79. * platform, all inclusive, including multiplexed channels. The available
  80. * physical channels will be multiplexed around these signals as they are
  81. * requested, just enumerate all possible channels.
  82. * @num_slave_channels: number of elements in the slave channel array
  83. * @memcpy_burst_size: the appropriate burst size for memcpy operations
  84. * @memcpy_bus_width: memory bus width
  85. * @memcpy_prot_buff: whether memcpy DMA is bufferable
  86. * @memcpy_prot_cache: whether memcpy DMA is cacheable
  87. * @get_xfer_signal: request a physical signal to be used for a DMA transfer
  88. * immediately: if there is some multiplexing or similar blocking the use
  89. * of the channel the transfer can be denied by returning less than zero,
  90. * else it returns the allocated signal number
  91. * @put_xfer_signal: indicate to the platform that this physical signal is not
  92. * running any DMA transfer and multiplexing can be recycled
  93. * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
  94. * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
  95. * @slave_map: DMA slave matching table
  96. * @slave_map_len: number of elements in @slave_map
  97. */
  98. struct pl08x_platform_data {
  99. struct pl08x_channel_data *slave_channels;
  100. unsigned int num_slave_channels;
  101. enum pl08x_burst_size memcpy_burst_size;
  102. enum pl08x_bus_width memcpy_bus_width;
  103. bool memcpy_prot_buff;
  104. bool memcpy_prot_cache;
  105. int (*get_xfer_signal)(const struct pl08x_channel_data *);
  106. void (*put_xfer_signal)(const struct pl08x_channel_data *, int);
  107. u8 lli_buses;
  108. u8 mem_buses;
  109. const struct dma_slave_map *slave_map;
  110. int slave_map_len;
  111. };
  112. #ifdef CONFIG_AMBA_PL08X
  113. bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
  114. #else
  115. static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
  116. {
  117. return false;
  118. }
  119. #endif
  120. #endif /* AMBA_PL08X_H */