pl080.h 7.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* include/linux/amba/pl080.h
  3. *
  4. * Copyright 2008 Openmoko, Inc.
  5. * Copyright 2008 Simtec Electronics
  6. * http://armlinux.simtec.co.uk/
  7. * Ben Dooks <ben@simtec.co.uk>
  8. *
  9. * ARM PrimeCell PL080 DMA controller
  10. */
  11. /* Note, there are some Samsung updates to this controller block which
  12. * make it not entierly compatible with the PL080 specification from
  13. * ARM. When in doubt, check the Samsung documentation first.
  14. *
  15. * The Samsung defines are PL080S, and add an extra control register,
  16. * the ability to move more than 2^11 counts of data and some extra
  17. * OneNAND features.
  18. */
  19. #ifndef ASM_PL080_H
  20. #define ASM_PL080_H
  21. #define PL080_INT_STATUS (0x00)
  22. #define PL080_TC_STATUS (0x04)
  23. #define PL080_TC_CLEAR (0x08)
  24. #define PL080_ERR_STATUS (0x0C)
  25. #define PL080_ERR_CLEAR (0x10)
  26. #define PL080_RAW_TC_STATUS (0x14)
  27. #define PL080_RAW_ERR_STATUS (0x18)
  28. #define PL080_EN_CHAN (0x1c)
  29. #define PL080_SOFT_BREQ (0x20)
  30. #define PL080_SOFT_SREQ (0x24)
  31. #define PL080_SOFT_LBREQ (0x28)
  32. #define PL080_SOFT_LSREQ (0x2C)
  33. #define PL080_CONFIG (0x30)
  34. #define PL080_CONFIG_M2_BE BIT(2)
  35. #define PL080_CONFIG_M1_BE BIT(1)
  36. #define PL080_CONFIG_ENABLE BIT(0)
  37. #define PL080_SYNC (0x34)
  38. /* The Faraday Technology FTDMAC020 variant registers */
  39. #define FTDMAC020_CH_BUSY (0x20)
  40. /* Identical to PL080_CONFIG */
  41. #define FTDMAC020_CSR (0x24)
  42. /* Identical to PL080_SYNC */
  43. #define FTDMAC020_SYNC (0x2C)
  44. #define FTDMAC020_REVISION (0x30)
  45. #define FTDMAC020_FEATURE (0x34)
  46. /* Per channel configuration registers */
  47. #define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
  48. #define PL080_CH_SRC_ADDR (0x00)
  49. #define PL080_CH_DST_ADDR (0x04)
  50. #define PL080_CH_LLI (0x08)
  51. #define PL080_CH_CONTROL (0x0C)
  52. #define PL080_CH_CONFIG (0x10)
  53. #define PL080S_CH_CONTROL2 (0x10)
  54. #define PL080S_CH_CONFIG (0x14)
  55. /* The Faraday FTDMAC020 derivative shuffles the registers around */
  56. #define FTDMAC020_CH_CSR (0x00)
  57. #define FTDMAC020_CH_CFG (0x04)
  58. #define FTDMAC020_CH_SRC_ADDR (0x08)
  59. #define FTDMAC020_CH_DST_ADDR (0x0C)
  60. #define FTDMAC020_CH_LLP (0x10)
  61. #define FTDMAC020_CH_SIZE (0x14)
  62. #define PL080_LLI_ADDR_MASK GENMASK(31, 2)
  63. #define PL080_LLI_ADDR_SHIFT (2)
  64. #define PL080_LLI_LM_AHB2 BIT(0)
  65. #define PL080_CONTROL_TC_IRQ_EN BIT(31)
  66. #define PL080_CONTROL_PROT_MASK GENMASK(30, 28)
  67. #define PL080_CONTROL_PROT_SHIFT (28)
  68. #define PL080_CONTROL_PROT_CACHE BIT(30)
  69. #define PL080_CONTROL_PROT_BUFF BIT(29)
  70. #define PL080_CONTROL_PROT_SYS BIT(28)
  71. #define PL080_CONTROL_DST_INCR BIT(27)
  72. #define PL080_CONTROL_SRC_INCR BIT(26)
  73. #define PL080_CONTROL_DST_AHB2 BIT(25)
  74. #define PL080_CONTROL_SRC_AHB2 BIT(24)
  75. #define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)
  76. #define PL080_CONTROL_DWIDTH_SHIFT (21)
  77. #define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)
  78. #define PL080_CONTROL_SWIDTH_SHIFT (18)
  79. #define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)
  80. #define PL080_CONTROL_DB_SIZE_SHIFT (15)
  81. #define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)
  82. #define PL080_CONTROL_SB_SIZE_SHIFT (12)
  83. #define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)
  84. #define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)
  85. #define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
  86. #define PL080_BSIZE_1 (0x0)
  87. #define PL080_BSIZE_4 (0x1)
  88. #define PL080_BSIZE_8 (0x2)
  89. #define PL080_BSIZE_16 (0x3)
  90. #define PL080_BSIZE_32 (0x4)
  91. #define PL080_BSIZE_64 (0x5)
  92. #define PL080_BSIZE_128 (0x6)
  93. #define PL080_BSIZE_256 (0x7)
  94. #define PL080_WIDTH_8BIT (0x0)
  95. #define PL080_WIDTH_16BIT (0x1)
  96. #define PL080_WIDTH_32BIT (0x2)
  97. #define PL080N_CONFIG_ITPROT BIT(20)
  98. #define PL080N_CONFIG_SECPROT BIT(19)
  99. #define PL080_CONFIG_HALT BIT(18)
  100. #define PL080_CONFIG_ACTIVE BIT(17) /* RO */
  101. #define PL080_CONFIG_LOCK BIT(16)
  102. #define PL080_CONFIG_TC_IRQ_MASK BIT(15)
  103. #define PL080_CONFIG_ERR_IRQ_MASK BIT(14)
  104. #define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)
  105. #define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
  106. #define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)
  107. #define PL080_CONFIG_DST_SEL_SHIFT (6)
  108. #define PL080_CONFIG_SRC_SEL_MASK GENMASK(4, 1)
  109. #define PL080_CONFIG_SRC_SEL_SHIFT (1)
  110. #define PL080_CONFIG_ENABLE BIT(0)
  111. #define PL080_FLOW_MEM2MEM (0x0)
  112. #define PL080_FLOW_MEM2PER (0x1)
  113. #define PL080_FLOW_PER2MEM (0x2)
  114. #define PL080_FLOW_SRC2DST (0x3)
  115. #define PL080_FLOW_SRC2DST_DST (0x4)
  116. #define PL080_FLOW_MEM2PER_PER (0x5)
  117. #define PL080_FLOW_PER2MEM_PER (0x6)
  118. #define PL080_FLOW_SRC2DST_SRC (0x7)
  119. #define FTDMAC020_CH_CSR_TC_MSK BIT(31)
  120. /* Later versions have a threshold in bits 24..26, */
  121. #define FTDMAC020_CH_CSR_FIFOTH_MSK GENMASK(26, 24)
  122. #define FTDMAC020_CH_CSR_FIFOTH_SHIFT (24)
  123. #define FTDMAC020_CH_CSR_CHPR1_MSK GENMASK(23, 22)
  124. #define FTDMAC020_CH_CSR_PROT3 BIT(21)
  125. #define FTDMAC020_CH_CSR_PROT2 BIT(20)
  126. #define FTDMAC020_CH_CSR_PROT1 BIT(19)
  127. #define FTDMAC020_CH_CSR_SRC_SIZE_MSK GENMASK(18, 16)
  128. #define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16)
  129. #define FTDMAC020_CH_CSR_ABT BIT(15)
  130. #define FTDMAC020_CH_CSR_SRC_WIDTH_MSK GENMASK(13, 11)
  131. #define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11)
  132. #define FTDMAC020_CH_CSR_DST_WIDTH_MSK GENMASK(10, 8)
  133. #define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8)
  134. #define FTDMAC020_CH_CSR_MODE BIT(7)
  135. /* 00 = increase, 01 = decrease, 10 = fix */
  136. #define FTDMAC020_CH_CSR_SRCAD_CTL_MSK GENMASK(6, 5)
  137. #define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5)
  138. #define FTDMAC020_CH_CSR_DSTAD_CTL_MSK GENMASK(4, 3)
  139. #define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3)
  140. #define FTDMAC020_CH_CSR_SRC_SEL BIT(2)
  141. #define FTDMAC020_CH_CSR_DST_SEL BIT(1)
  142. #define FTDMAC020_CH_CSR_EN BIT(0)
  143. /* FIFO threshold setting */
  144. #define FTDMAC020_CH_CSR_FIFOTH_1 (0x0)
  145. #define FTDMAC020_CH_CSR_FIFOTH_2 (0x1)
  146. #define FTDMAC020_CH_CSR_FIFOTH_4 (0x2)
  147. #define FTDMAC020_CH_CSR_FIFOTH_8 (0x3)
  148. #define FTDMAC020_CH_CSR_FIFOTH_16 (0x4)
  149. /* The FTDMAC020 supports 64bit wide transfers */
  150. #define FTDMAC020_WIDTH_64BIT (0x3)
  151. /* Address can be increased, decreased or fixed */
  152. #define FTDMAC020_CH_CSR_SRCAD_CTL_INC (0x0)
  153. #define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1)
  154. #define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2)
  155. #define FTDMAC020_CH_CFG_LLP_CNT_MASK GENMASK(19, 16)
  156. #define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16)
  157. #define FTDMAC020_CH_CFG_BUSY BIT(8)
  158. #define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2)
  159. #define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1)
  160. #define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0)
  161. /* Inside the LLIs, the applicable CSR fields are mapped differently */
  162. #define FTDMAC020_LLI_TC_MSK BIT(28)
  163. #define FTDMAC020_LLI_SRC_WIDTH_MSK GENMASK(27, 25)
  164. #define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25)
  165. #define FTDMAC020_LLI_DST_WIDTH_MSK GENMASK(24, 22)
  166. #define FTDMAC020_LLI_DST_WIDTH_SHIFT (22)
  167. #define FTDMAC020_LLI_SRCAD_CTL_MSK GENMASK(21, 20)
  168. #define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20)
  169. #define FTDMAC020_LLI_DSTAD_CTL_MSK GENMASK(19, 18)
  170. #define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18)
  171. #define FTDMAC020_LLI_SRC_SEL BIT(17)
  172. #define FTDMAC020_LLI_DST_SEL BIT(16)
  173. #define FTDMAC020_LLI_TRANSFER_SIZE_MASK GENMASK(11, 0)
  174. #define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0)
  175. #define FTDMAC020_CFG_LLP_CNT_MASK GENMASK(19, 16)
  176. #define FTDMAC020_CFG_LLP_CNT_SHIFT (16)
  177. #define FTDMAC020_CFG_BUSY BIT(8)
  178. #define FTDMAC020_CFG_INT_ABT_MSK BIT(2)
  179. #define FTDMAC020_CFG_INT_ERR_MSK BIT(1)
  180. #define FTDMAC020_CFG_INT_TC_MSK BIT(0)
  181. /* DMA linked list chain structure */
  182. struct pl080_lli {
  183. u32 src_addr;
  184. u32 dst_addr;
  185. u32 next_lli;
  186. u32 control0;
  187. };
  188. struct pl080s_lli {
  189. u32 src_addr;
  190. u32 dst_addr;
  191. u32 next_lli;
  192. u32 control0;
  193. u32 control1;
  194. };
  195. #endif /* ASM_PL080_H */