pl022.h 8.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * include/linux/amba/pl022.h
  4. *
  5. * Copyright (C) 2008-2009 ST-Ericsson AB
  6. * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
  7. *
  8. * Author: Linus Walleij <linus.walleij@stericsson.com>
  9. *
  10. * Initial version inspired by:
  11. * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
  12. * Initial adoption to PL022 by:
  13. * Sachin Verma <sachin.verma@st.com>
  14. */
  15. #ifndef _SSP_PL022_H
  16. #define _SSP_PL022_H
  17. #include <linux/types.h>
  18. /**
  19. * whether SSP is in loopback mode or not
  20. */
  21. enum ssp_loopback {
  22. LOOPBACK_DISABLED,
  23. LOOPBACK_ENABLED
  24. };
  25. /**
  26. * enum ssp_interface - interfaces allowed for this SSP Controller
  27. * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
  28. * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
  29. * interface
  30. * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
  31. * interface
  32. * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
  33. * &STn8815 only)
  34. */
  35. enum ssp_interface {
  36. SSP_INTERFACE_MOTOROLA_SPI,
  37. SSP_INTERFACE_TI_SYNC_SERIAL,
  38. SSP_INTERFACE_NATIONAL_MICROWIRE,
  39. SSP_INTERFACE_UNIDIRECTIONAL
  40. };
  41. /**
  42. * enum ssp_hierarchy - whether SSP is configured as Master or Slave
  43. */
  44. enum ssp_hierarchy {
  45. SSP_MASTER,
  46. SSP_SLAVE
  47. };
  48. /**
  49. * enum ssp_clock_params - clock parameters, to set SSP clock at a
  50. * desired freq
  51. */
  52. struct ssp_clock_params {
  53. u8 cpsdvsr; /* value from 2 to 254 (even only!) */
  54. u8 scr; /* value from 0 to 255 */
  55. };
  56. /**
  57. * enum ssp_rx_endian - endianess of Rx FIFO Data
  58. * this feature is only available in ST versionf of PL022
  59. */
  60. enum ssp_rx_endian {
  61. SSP_RX_MSB,
  62. SSP_RX_LSB
  63. };
  64. /**
  65. * enum ssp_tx_endian - endianess of Tx FIFO Data
  66. */
  67. enum ssp_tx_endian {
  68. SSP_TX_MSB,
  69. SSP_TX_LSB
  70. };
  71. /**
  72. * enum ssp_data_size - number of bits in one data element
  73. */
  74. enum ssp_data_size {
  75. SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
  76. SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
  77. SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
  78. SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
  79. SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
  80. SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
  81. SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
  82. SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
  83. SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
  84. SSP_DATA_BITS_31, SSP_DATA_BITS_32
  85. };
  86. /**
  87. * enum ssp_mode - SSP mode of operation (Communication modes)
  88. */
  89. enum ssp_mode {
  90. INTERRUPT_TRANSFER,
  91. POLLING_TRANSFER,
  92. DMA_TRANSFER
  93. };
  94. /**
  95. * enum ssp_rx_level_trig - receive FIFO watermark level which triggers
  96. * IT: Interrupt fires when _N_ or more elements in RX FIFO.
  97. */
  98. enum ssp_rx_level_trig {
  99. SSP_RX_1_OR_MORE_ELEM,
  100. SSP_RX_4_OR_MORE_ELEM,
  101. SSP_RX_8_OR_MORE_ELEM,
  102. SSP_RX_16_OR_MORE_ELEM,
  103. SSP_RX_32_OR_MORE_ELEM
  104. };
  105. /**
  106. * Transmit FIFO watermark level which triggers (IT Interrupt fires
  107. * when _N_ or more empty locations in TX FIFO)
  108. */
  109. enum ssp_tx_level_trig {
  110. SSP_TX_1_OR_MORE_EMPTY_LOC,
  111. SSP_TX_4_OR_MORE_EMPTY_LOC,
  112. SSP_TX_8_OR_MORE_EMPTY_LOC,
  113. SSP_TX_16_OR_MORE_EMPTY_LOC,
  114. SSP_TX_32_OR_MORE_EMPTY_LOC
  115. };
  116. /**
  117. * enum SPI Clock Phase - clock phase (Motorola SPI interface only)
  118. * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity)
  119. * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity)
  120. */
  121. enum ssp_spi_clk_phase {
  122. SSP_CLK_FIRST_EDGE,
  123. SSP_CLK_SECOND_EDGE
  124. };
  125. /**
  126. * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only)
  127. * @SSP_CLK_POL_IDLE_LOW: Low inactive level
  128. * @SSP_CLK_POL_IDLE_HIGH: High inactive level
  129. */
  130. enum ssp_spi_clk_pol {
  131. SSP_CLK_POL_IDLE_LOW,
  132. SSP_CLK_POL_IDLE_HIGH
  133. };
  134. /**
  135. * Microwire Conrol Lengths Command size in microwire format
  136. */
  137. enum ssp_microwire_ctrl_len {
  138. SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6,
  139. SSP_BITS_7, SSP_BITS_8, SSP_BITS_9,
  140. SSP_BITS_10, SSP_BITS_11, SSP_BITS_12,
  141. SSP_BITS_13, SSP_BITS_14, SSP_BITS_15,
  142. SSP_BITS_16, SSP_BITS_17, SSP_BITS_18,
  143. SSP_BITS_19, SSP_BITS_20, SSP_BITS_21,
  144. SSP_BITS_22, SSP_BITS_23, SSP_BITS_24,
  145. SSP_BITS_25, SSP_BITS_26, SSP_BITS_27,
  146. SSP_BITS_28, SSP_BITS_29, SSP_BITS_30,
  147. SSP_BITS_31, SSP_BITS_32
  148. };
  149. /**
  150. * enum Microwire Wait State
  151. * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit
  152. * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit
  153. */
  154. enum ssp_microwire_wait_state {
  155. SSP_MWIRE_WAIT_ZERO,
  156. SSP_MWIRE_WAIT_ONE
  157. };
  158. /**
  159. * enum ssp_duplex - whether Full/Half Duplex on microwire, only
  160. * available in the ST Micro variant.
  161. * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
  162. * SSPRXD not used
  163. * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
  164. * an input.
  165. */
  166. enum ssp_duplex {
  167. SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
  168. SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
  169. };
  170. /**
  171. * enum ssp_clkdelay - an optional clock delay on the feedback clock
  172. * only available in the ST Micro PL023 variant.
  173. * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
  174. * slave is sampled directly
  175. * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
  176. * a delay of T-dt
  177. * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
  178. * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
  179. * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
  180. * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
  181. * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
  182. * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
  183. */
  184. enum ssp_clkdelay {
  185. SSP_FEEDBACK_CLK_DELAY_NONE,
  186. SSP_FEEDBACK_CLK_DELAY_1T,
  187. SSP_FEEDBACK_CLK_DELAY_2T,
  188. SSP_FEEDBACK_CLK_DELAY_3T,
  189. SSP_FEEDBACK_CLK_DELAY_4T,
  190. SSP_FEEDBACK_CLK_DELAY_5T,
  191. SSP_FEEDBACK_CLK_DELAY_6T,
  192. SSP_FEEDBACK_CLK_DELAY_7T
  193. };
  194. /**
  195. * CHIP select/deselect commands
  196. */
  197. enum ssp_chip_select {
  198. SSP_CHIP_SELECT,
  199. SSP_CHIP_DESELECT
  200. };
  201. struct dma_chan;
  202. /**
  203. * struct pl022_ssp_master - device.platform_data for SPI controller devices.
  204. * @bus_id: identifier for this bus
  205. * @num_chipselect: chipselects are used to distinguish individual
  206. * SPI slaves, and are numbered from zero to num_chipselects - 1.
  207. * each slave has a chipselect signal, but it's common that not
  208. * every chipselect is connected to a slave.
  209. * @enable_dma: if true enables DMA driven transfers.
  210. * @dma_rx_param: parameter to locate an RX DMA channel.
  211. * @dma_tx_param: parameter to locate a TX DMA channel.
  212. * @autosuspend_delay: delay in ms following transfer completion before the
  213. * runtime power management system suspends the device. A setting of 0
  214. * indicates no delay and the device will be suspended immediately.
  215. * @rt: indicates the controller should run the message pump with realtime
  216. * priority to minimise the transfer latency on the bus.
  217. * @chipselects: list of <num_chipselects> chip select gpios
  218. */
  219. struct pl022_ssp_controller {
  220. u16 bus_id;
  221. u8 num_chipselect;
  222. u8 enable_dma:1;
  223. bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
  224. void *dma_rx_param;
  225. void *dma_tx_param;
  226. int autosuspend_delay;
  227. bool rt;
  228. int *chipselects;
  229. };
  230. /**
  231. * struct ssp_config_chip - spi_board_info.controller_data for SPI
  232. * slave devices, copied to spi_device.controller_data.
  233. *
  234. * @iface: Interface type(Motorola, TI, Microwire, Universal)
  235. * @hierarchy: sets whether interface is master or slave
  236. * @slave_tx_disable: SSPTXD is disconnected (in slave mode only)
  237. * @clk_freq: Tune freq parameters of SSP(when in master mode)
  238. * @com_mode: communication mode: polling, Interrupt or DMA
  239. * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode)
  240. * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode)
  241. * @ctrl_len: Microwire interface: Control length
  242. * @wait_state: Microwire interface: Wait state
  243. * @duplex: Microwire interface: Full/Half duplex
  244. * @clkdelay: on the PL023 variant, the delay in feeback clock cycles
  245. * before sampling the incoming line
  246. * @cs_control: function pointer to board-specific function to
  247. * assert/deassert I/O port to control HW generation of devices chip-select.
  248. */
  249. struct pl022_config_chip {
  250. enum ssp_interface iface;
  251. enum ssp_hierarchy hierarchy;
  252. bool slave_tx_disable;
  253. struct ssp_clock_params clk_freq;
  254. enum ssp_mode com_mode;
  255. enum ssp_rx_level_trig rx_lev_trig;
  256. enum ssp_tx_level_trig tx_lev_trig;
  257. enum ssp_microwire_ctrl_len ctrl_len;
  258. enum ssp_microwire_wait_state wait_state;
  259. enum ssp_duplex duplex;
  260. enum ssp_clkdelay clkdelay;
  261. void (*cs_control) (u32 control);
  262. };
  263. #endif /* _SSP_PL022_H */