xlnx-zynqmp-resets.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2018 Xilinx, Inc.
  4. */
  5. #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
  6. #define _DT_BINDINGS_ZYNQMP_RESETS_H
  7. #define ZYNQMP_RESET_PCIE_CFG 0
  8. #define ZYNQMP_RESET_PCIE_BRIDGE 1
  9. #define ZYNQMP_RESET_PCIE_CTRL 2
  10. #define ZYNQMP_RESET_DP 3
  11. #define ZYNQMP_RESET_SWDT_CRF 4
  12. #define ZYNQMP_RESET_AFI_FM5 5
  13. #define ZYNQMP_RESET_AFI_FM4 6
  14. #define ZYNQMP_RESET_AFI_FM3 7
  15. #define ZYNQMP_RESET_AFI_FM2 8
  16. #define ZYNQMP_RESET_AFI_FM1 9
  17. #define ZYNQMP_RESET_AFI_FM0 10
  18. #define ZYNQMP_RESET_GDMA 11
  19. #define ZYNQMP_RESET_GPU_PP1 12
  20. #define ZYNQMP_RESET_GPU_PP0 13
  21. #define ZYNQMP_RESET_GPU 14
  22. #define ZYNQMP_RESET_GT 15
  23. #define ZYNQMP_RESET_SATA 16
  24. #define ZYNQMP_RESET_ACPU3_PWRON 17
  25. #define ZYNQMP_RESET_ACPU2_PWRON 18
  26. #define ZYNQMP_RESET_ACPU1_PWRON 19
  27. #define ZYNQMP_RESET_ACPU0_PWRON 20
  28. #define ZYNQMP_RESET_APU_L2 21
  29. #define ZYNQMP_RESET_ACPU3 22
  30. #define ZYNQMP_RESET_ACPU2 23
  31. #define ZYNQMP_RESET_ACPU1 24
  32. #define ZYNQMP_RESET_ACPU0 25
  33. #define ZYNQMP_RESET_DDR 26
  34. #define ZYNQMP_RESET_APM_FPD 27
  35. #define ZYNQMP_RESET_SOFT 28
  36. #define ZYNQMP_RESET_GEM0 29
  37. #define ZYNQMP_RESET_GEM1 30
  38. #define ZYNQMP_RESET_GEM2 31
  39. #define ZYNQMP_RESET_GEM3 32
  40. #define ZYNQMP_RESET_QSPI 33
  41. #define ZYNQMP_RESET_UART0 34
  42. #define ZYNQMP_RESET_UART1 35
  43. #define ZYNQMP_RESET_SPI0 36
  44. #define ZYNQMP_RESET_SPI1 37
  45. #define ZYNQMP_RESET_SDIO0 38
  46. #define ZYNQMP_RESET_SDIO1 39
  47. #define ZYNQMP_RESET_CAN0 40
  48. #define ZYNQMP_RESET_CAN1 41
  49. #define ZYNQMP_RESET_I2C0 42
  50. #define ZYNQMP_RESET_I2C1 43
  51. #define ZYNQMP_RESET_TTC0 44
  52. #define ZYNQMP_RESET_TTC1 45
  53. #define ZYNQMP_RESET_TTC2 46
  54. #define ZYNQMP_RESET_TTC3 47
  55. #define ZYNQMP_RESET_SWDT_CRL 48
  56. #define ZYNQMP_RESET_NAND 49
  57. #define ZYNQMP_RESET_ADMA 50
  58. #define ZYNQMP_RESET_GPIO 51
  59. #define ZYNQMP_RESET_IOU_CC 52
  60. #define ZYNQMP_RESET_TIMESTAMP 53
  61. #define ZYNQMP_RESET_RPU_R50 54
  62. #define ZYNQMP_RESET_RPU_R51 55
  63. #define ZYNQMP_RESET_RPU_AMBA 56
  64. #define ZYNQMP_RESET_OCM 57
  65. #define ZYNQMP_RESET_RPU_PGE 58
  66. #define ZYNQMP_RESET_USB0_CORERESET 59
  67. #define ZYNQMP_RESET_USB1_CORERESET 60
  68. #define ZYNQMP_RESET_USB0_HIBERRESET 61
  69. #define ZYNQMP_RESET_USB1_HIBERRESET 62
  70. #define ZYNQMP_RESET_USB0_APB 63
  71. #define ZYNQMP_RESET_USB1_APB 64
  72. #define ZYNQMP_RESET_IPI 65
  73. #define ZYNQMP_RESET_APM_LPD 66
  74. #define ZYNQMP_RESET_RTC 67
  75. #define ZYNQMP_RESET_SYSMON 68
  76. #define ZYNQMP_RESET_AFI_FM6 69
  77. #define ZYNQMP_RESET_LPD_SWDT 70
  78. #define ZYNQMP_RESET_FPD 71
  79. #define ZYNQMP_RESET_RPU_DBG1 72
  80. #define ZYNQMP_RESET_RPU_DBG0 73
  81. #define ZYNQMP_RESET_DBG_LPD 74
  82. #define ZYNQMP_RESET_DBG_FPD 75
  83. #define ZYNQMP_RESET_APLL 76
  84. #define ZYNQMP_RESET_DPLL 77
  85. #define ZYNQMP_RESET_VPLL 78
  86. #define ZYNQMP_RESET_IOPLL 79
  87. #define ZYNQMP_RESET_RPLL 80
  88. #define ZYNQMP_RESET_GPO3_PL_0 81
  89. #define ZYNQMP_RESET_GPO3_PL_1 82
  90. #define ZYNQMP_RESET_GPO3_PL_2 83
  91. #define ZYNQMP_RESET_GPO3_PL_3 84
  92. #define ZYNQMP_RESET_GPO3_PL_4 85
  93. #define ZYNQMP_RESET_GPO3_PL_5 86
  94. #define ZYNQMP_RESET_GPO3_PL_6 87
  95. #define ZYNQMP_RESET_GPO3_PL_7 88
  96. #define ZYNQMP_RESET_GPO3_PL_8 89
  97. #define ZYNQMP_RESET_GPO3_PL_9 90
  98. #define ZYNQMP_RESET_GPO3_PL_10 91
  99. #define ZYNQMP_RESET_GPO3_PL_11 92
  100. #define ZYNQMP_RESET_GPO3_PL_12 93
  101. #define ZYNQMP_RESET_GPO3_PL_13 94
  102. #define ZYNQMP_RESET_GPO3_PL_14 95
  103. #define ZYNQMP_RESET_GPO3_PL_15 96
  104. #define ZYNQMP_RESET_GPO3_PL_16 97
  105. #define ZYNQMP_RESET_GPO3_PL_17 98
  106. #define ZYNQMP_RESET_GPO3_PL_18 99
  107. #define ZYNQMP_RESET_GPO3_PL_19 100
  108. #define ZYNQMP_RESET_GPO3_PL_20 101
  109. #define ZYNQMP_RESET_GPO3_PL_21 102
  110. #define ZYNQMP_RESET_GPO3_PL_22 103
  111. #define ZYNQMP_RESET_GPO3_PL_23 104
  112. #define ZYNQMP_RESET_GPO3_PL_24 105
  113. #define ZYNQMP_RESET_GPO3_PL_25 106
  114. #define ZYNQMP_RESET_GPO3_PL_26 107
  115. #define ZYNQMP_RESET_GPO3_PL_27 108
  116. #define ZYNQMP_RESET_GPO3_PL_28 109
  117. #define ZYNQMP_RESET_GPO3_PL_29 110
  118. #define ZYNQMP_RESET_GPO3_PL_30 111
  119. #define ZYNQMP_RESET_GPO3_PL_31 112
  120. #define ZYNQMP_RESET_RPU_LS 113
  121. #define ZYNQMP_RESET_PS_ONLY 114
  122. #define ZYNQMP_RESET_PL 115
  123. #define ZYNQMP_RESET_PS_PL0 116
  124. #define ZYNQMP_RESET_PS_PL1 117
  125. #define ZYNQMP_RESET_PS_PL2 118
  126. #define ZYNQMP_RESET_PS_PL3 119
  127. #endif