qcom,gcc-ipq806x.h 5.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DT_BINDINGS_RESET_IPQ_806X_H
  6. #define _DT_BINDINGS_RESET_IPQ_806X_H
  7. #define QDSS_STM_RESET 0
  8. #define AFAB_SMPSS_S_RESET 1
  9. #define AFAB_SMPSS_M1_RESET 2
  10. #define AFAB_SMPSS_M0_RESET 3
  11. #define AFAB_EBI1_CH0_RESET 4
  12. #define AFAB_EBI1_CH1_RESET 5
  13. #define SFAB_ADM0_M0_RESET 6
  14. #define SFAB_ADM0_M1_RESET 7
  15. #define SFAB_ADM0_M2_RESET 8
  16. #define ADM0_C2_RESET 9
  17. #define ADM0_C1_RESET 10
  18. #define ADM0_C0_RESET 11
  19. #define ADM0_PBUS_RESET 12
  20. #define ADM0_RESET 13
  21. #define QDSS_CLKS_SW_RESET 14
  22. #define QDSS_POR_RESET 15
  23. #define QDSS_TSCTR_RESET 16
  24. #define QDSS_HRESET_RESET 17
  25. #define QDSS_AXI_RESET 18
  26. #define QDSS_DBG_RESET 19
  27. #define SFAB_PCIE_M_RESET 20
  28. #define SFAB_PCIE_S_RESET 21
  29. #define PCIE_EXT_RESET 22
  30. #define PCIE_PHY_RESET 23
  31. #define PCIE_PCI_RESET 24
  32. #define PCIE_POR_RESET 25
  33. #define PCIE_HCLK_RESET 26
  34. #define PCIE_ACLK_RESET 27
  35. #define SFAB_LPASS_RESET 28
  36. #define SFAB_AFAB_M_RESET 29
  37. #define AFAB_SFAB_M0_RESET 30
  38. #define AFAB_SFAB_M1_RESET 31
  39. #define SFAB_SATA_S_RESET 32
  40. #define SFAB_DFAB_M_RESET 33
  41. #define DFAB_SFAB_M_RESET 34
  42. #define DFAB_SWAY0_RESET 35
  43. #define DFAB_SWAY1_RESET 36
  44. #define DFAB_ARB0_RESET 37
  45. #define DFAB_ARB1_RESET 38
  46. #define PPSS_PROC_RESET 39
  47. #define PPSS_RESET 40
  48. #define DMA_BAM_RESET 41
  49. #define SPS_TIC_H_RESET 42
  50. #define SFAB_CFPB_M_RESET 43
  51. #define SFAB_CFPB_S_RESET 44
  52. #define TSIF_H_RESET 45
  53. #define CE1_H_RESET 46
  54. #define CE1_CORE_RESET 47
  55. #define CE1_SLEEP_RESET 48
  56. #define CE2_H_RESET 49
  57. #define CE2_CORE_RESET 50
  58. #define SFAB_SFPB_M_RESET 51
  59. #define SFAB_SFPB_S_RESET 52
  60. #define RPM_PROC_RESET 53
  61. #define PMIC_SSBI2_RESET 54
  62. #define SDC1_RESET 55
  63. #define SDC2_RESET 56
  64. #define SDC3_RESET 57
  65. #define SDC4_RESET 58
  66. #define USB_HS1_RESET 59
  67. #define USB_HSIC_RESET 60
  68. #define USB_FS1_XCVR_RESET 61
  69. #define USB_FS1_RESET 62
  70. #define GSBI1_RESET 63
  71. #define GSBI2_RESET 64
  72. #define GSBI3_RESET 65
  73. #define GSBI4_RESET 66
  74. #define GSBI5_RESET 67
  75. #define GSBI6_RESET 68
  76. #define GSBI7_RESET 69
  77. #define SPDM_RESET 70
  78. #define SEC_CTRL_RESET 71
  79. #define TLMM_H_RESET 72
  80. #define SFAB_SATA_M_RESET 73
  81. #define SATA_RESET 74
  82. #define TSSC_RESET 75
  83. #define PDM_RESET 76
  84. #define MPM_H_RESET 77
  85. #define MPM_RESET 78
  86. #define SFAB_SMPSS_S_RESET 79
  87. #define PRNG_RESET 80
  88. #define SFAB_CE3_M_RESET 81
  89. #define SFAB_CE3_S_RESET 82
  90. #define CE3_SLEEP_RESET 83
  91. #define PCIE_1_M_RESET 84
  92. #define PCIE_1_S_RESET 85
  93. #define PCIE_1_EXT_RESET 86
  94. #define PCIE_1_PHY_RESET 87
  95. #define PCIE_1_PCI_RESET 88
  96. #define PCIE_1_POR_RESET 89
  97. #define PCIE_1_HCLK_RESET 90
  98. #define PCIE_1_ACLK_RESET 91
  99. #define PCIE_2_M_RESET 92
  100. #define PCIE_2_S_RESET 93
  101. #define PCIE_2_EXT_RESET 94
  102. #define PCIE_2_PHY_RESET 95
  103. #define PCIE_2_PCI_RESET 96
  104. #define PCIE_2_POR_RESET 97
  105. #define PCIE_2_HCLK_RESET 98
  106. #define PCIE_2_ACLK_RESET 99
  107. #define SFAB_USB30_S_RESET 100
  108. #define SFAB_USB30_M_RESET 101
  109. #define USB30_0_PORT2_HS_PHY_RESET 102
  110. #define USB30_0_MASTER_RESET 103
  111. #define USB30_0_SLEEP_RESET 104
  112. #define USB30_0_UTMI_PHY_RESET 105
  113. #define USB30_0_POWERON_RESET 106
  114. #define USB30_0_PHY_RESET 107
  115. #define USB30_1_MASTER_RESET 108
  116. #define USB30_1_SLEEP_RESET 109
  117. #define USB30_1_UTMI_PHY_RESET 110
  118. #define USB30_1_POWERON_RESET 111
  119. #define USB30_1_PHY_RESET 112
  120. #define NSSFB0_RESET 113
  121. #define NSSFB1_RESET 114
  122. #define UBI32_CORE1_CLKRST_CLAMP_RESET 115
  123. #define UBI32_CORE1_CLAMP_RESET 116
  124. #define UBI32_CORE1_AHB_RESET 117
  125. #define UBI32_CORE1_AXI_RESET 118
  126. #define UBI32_CORE2_CLKRST_CLAMP_RESET 119
  127. #define UBI32_CORE2_CLAMP_RESET 120
  128. #define UBI32_CORE2_AHB_RESET 121
  129. #define UBI32_CORE2_AXI_RESET 122
  130. #define GMAC_CORE1_RESET 123
  131. #define GMAC_CORE2_RESET 124
  132. #define GMAC_CORE3_RESET 125
  133. #define GMAC_CORE4_RESET 126
  134. #define GMAC_AHB_RESET 127
  135. #define NSS_CH0_RST_RX_CLK_N_RESET 128
  136. #define NSS_CH0_RST_TX_CLK_N_RESET 129
  137. #define NSS_CH0_RST_RX_125M_N_RESET 130
  138. #define NSS_CH0_HW_RST_RX_125M_N_RESET 131
  139. #define NSS_CH0_RST_TX_125M_N_RESET 132
  140. #define NSS_CH1_RST_RX_CLK_N_RESET 133
  141. #define NSS_CH1_RST_TX_CLK_N_RESET 134
  142. #define NSS_CH1_RST_RX_125M_N_RESET 135
  143. #define NSS_CH1_HW_RST_RX_125M_N_RESET 136
  144. #define NSS_CH1_RST_TX_125M_N_RESET 137
  145. #define NSS_CH2_RST_RX_CLK_N_RESET 138
  146. #define NSS_CH2_RST_TX_CLK_N_RESET 139
  147. #define NSS_CH2_RST_RX_125M_N_RESET 140
  148. #define NSS_CH2_HW_RST_RX_125M_N_RESET 141
  149. #define NSS_CH2_RST_TX_125M_N_RESET 142
  150. #define NSS_CH3_RST_RX_CLK_N_RESET 143
  151. #define NSS_CH3_RST_TX_CLK_N_RESET 144
  152. #define NSS_CH3_RST_RX_125M_N_RESET 145
  153. #define NSS_CH3_HW_RST_RX_125M_N_RESET 146
  154. #define NSS_CH3_RST_TX_125M_N_RESET 147
  155. #define NSS_RST_RX_250M_125M_N_RESET 148
  156. #define NSS_RST_TX_250M_125M_N_RESET 149
  157. #define NSS_QSGMII_TXPI_RST_N_RESET 150
  158. #define NSS_QSGMII_CDR_RST_N_RESET 151
  159. #define NSS_SGMII2_CDR_RST_N_RESET 152
  160. #define NSS_SGMII3_CDR_RST_N_RESET 153
  161. #define NSS_CAL_PRBS_RST_N_RESET 154
  162. #define NSS_LCKDT_RST_N_RESET 155
  163. #define NSS_SRDS_N_RESET 156
  164. #endif