qcom,gcc-apq8084.h 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H
  6. #define _DT_BINDINGS_RESET_APQ_GCC_8084_H
  7. #define GCC_SYSTEM_NOC_BCR 0
  8. #define GCC_CONFIG_NOC_BCR 1
  9. #define GCC_PERIPH_NOC_BCR 2
  10. #define GCC_IMEM_BCR 3
  11. #define GCC_MMSS_BCR 4
  12. #define GCC_QDSS_BCR 5
  13. #define GCC_USB_30_BCR 6
  14. #define GCC_USB3_PHY_BCR 7
  15. #define GCC_USB_HS_HSIC_BCR 8
  16. #define GCC_USB_HS_BCR 9
  17. #define GCC_USB2A_PHY_BCR 10
  18. #define GCC_USB2B_PHY_BCR 11
  19. #define GCC_SDCC1_BCR 12
  20. #define GCC_SDCC2_BCR 13
  21. #define GCC_SDCC3_BCR 14
  22. #define GCC_SDCC4_BCR 15
  23. #define GCC_BLSP1_BCR 16
  24. #define GCC_BLSP1_QUP1_BCR 17
  25. #define GCC_BLSP1_UART1_BCR 18
  26. #define GCC_BLSP1_QUP2_BCR 19
  27. #define GCC_BLSP1_UART2_BCR 20
  28. #define GCC_BLSP1_QUP3_BCR 21
  29. #define GCC_BLSP1_UART3_BCR 22
  30. #define GCC_BLSP1_QUP4_BCR 23
  31. #define GCC_BLSP1_UART4_BCR 24
  32. #define GCC_BLSP1_QUP5_BCR 25
  33. #define GCC_BLSP1_UART5_BCR 26
  34. #define GCC_BLSP1_QUP6_BCR 27
  35. #define GCC_BLSP1_UART6_BCR 28
  36. #define GCC_BLSP2_BCR 29
  37. #define GCC_BLSP2_QUP1_BCR 30
  38. #define GCC_BLSP2_UART1_BCR 31
  39. #define GCC_BLSP2_QUP2_BCR 32
  40. #define GCC_BLSP2_UART2_BCR 33
  41. #define GCC_BLSP2_QUP3_BCR 34
  42. #define GCC_BLSP2_UART3_BCR 35
  43. #define GCC_BLSP2_QUP4_BCR 36
  44. #define GCC_BLSP2_UART4_BCR 37
  45. #define GCC_BLSP2_QUP5_BCR 38
  46. #define GCC_BLSP2_UART5_BCR 39
  47. #define GCC_BLSP2_QUP6_BCR 40
  48. #define GCC_BLSP2_UART6_BCR 41
  49. #define GCC_PDM_BCR 42
  50. #define GCC_PRNG_BCR 43
  51. #define GCC_BAM_DMA_BCR 44
  52. #define GCC_TSIF_BCR 45
  53. #define GCC_TCSR_BCR 46
  54. #define GCC_BOOT_ROM_BCR 47
  55. #define GCC_MSG_RAM_BCR 48
  56. #define GCC_TLMM_BCR 49
  57. #define GCC_MPM_BCR 50
  58. #define GCC_MPM_AHB_RESET 51
  59. #define GCC_MPM_NON_AHB_RESET 52
  60. #define GCC_SEC_CTRL_BCR 53
  61. #define GCC_SPMI_BCR 54
  62. #define GCC_SPDM_BCR 55
  63. #define GCC_CE1_BCR 56
  64. #define GCC_CE2_BCR 57
  65. #define GCC_BIMC_BCR 58
  66. #define GCC_SNOC_BUS_TIMEOUT0_BCR 59
  67. #define GCC_SNOC_BUS_TIMEOUT2_BCR 60
  68. #define GCC_PNOC_BUS_TIMEOUT0_BCR 61
  69. #define GCC_PNOC_BUS_TIMEOUT1_BCR 62
  70. #define GCC_PNOC_BUS_TIMEOUT2_BCR 63
  71. #define GCC_PNOC_BUS_TIMEOUT3_BCR 64
  72. #define GCC_PNOC_BUS_TIMEOUT4_BCR 65
  73. #define GCC_CNOC_BUS_TIMEOUT0_BCR 66
  74. #define GCC_CNOC_BUS_TIMEOUT1_BCR 67
  75. #define GCC_CNOC_BUS_TIMEOUT2_BCR 68
  76. #define GCC_CNOC_BUS_TIMEOUT3_BCR 69
  77. #define GCC_CNOC_BUS_TIMEOUT4_BCR 70
  78. #define GCC_CNOC_BUS_TIMEOUT5_BCR 71
  79. #define GCC_CNOC_BUS_TIMEOUT6_BCR 72
  80. #define GCC_DEHR_BCR 73
  81. #define GCC_RBCPR_BCR 74
  82. #define GCC_MSS_RESTART 75
  83. #define GCC_LPASS_RESTART 76
  84. #define GCC_WCSS_RESTART 77
  85. #define GCC_VENUS_RESTART 78
  86. #define GCC_COPSS_SMMU_BCR 79
  87. #define GCC_SPSS_BCR 80
  88. #define GCC_PCIE_0_BCR 81
  89. #define GCC_PCIE_0_PHY_BCR 82
  90. #define GCC_PCIE_1_BCR 83
  91. #define GCC_PCIE_1_PHY_BCR 84
  92. #define GCC_USB_30_SEC_BCR 85
  93. #define GCC_USB3_SEC_PHY_BCR 86
  94. #define GCC_SATA_BCR 87
  95. #define GCC_CE3_BCR 88
  96. #define GCC_UFS_BCR 89
  97. #define GCC_USB30_PHY_COM_BCR 90
  98. #endif