12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091 |
- /* SPDX-License-Identifier: GPL-2.0 */
- // Copyright (c) 2019 Nuvoton Technology corporation.
- #ifndef _DT_BINDINGS_NPCM7XX_RESET_H
- #define _DT_BINDINGS_NPCM7XX_RESET_H
- #define NPCM7XX_RESET_IPSRST1 0x20
- #define NPCM7XX_RESET_IPSRST2 0x24
- #define NPCM7XX_RESET_IPSRST3 0x34
- /* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */
- #define NPCM7XX_RESET_FIU3 1
- #define NPCM7XX_RESET_UDC1 5
- #define NPCM7XX_RESET_EMC1 6
- #define NPCM7XX_RESET_UART_2_3 7
- #define NPCM7XX_RESET_UDC2 8
- #define NPCM7XX_RESET_PECI 9
- #define NPCM7XX_RESET_AES 10
- #define NPCM7XX_RESET_UART_0_1 11
- #define NPCM7XX_RESET_MC 12
- #define NPCM7XX_RESET_SMB2 13
- #define NPCM7XX_RESET_SMB3 14
- #define NPCM7XX_RESET_SMB4 15
- #define NPCM7XX_RESET_SMB5 16
- #define NPCM7XX_RESET_PWM_M0 18
- #define NPCM7XX_RESET_TIMER_0_4 19
- #define NPCM7XX_RESET_TIMER_5_9 20
- #define NPCM7XX_RESET_EMC2 21
- #define NPCM7XX_RESET_UDC4 22
- #define NPCM7XX_RESET_UDC5 23
- #define NPCM7XX_RESET_UDC6 24
- #define NPCM7XX_RESET_UDC3 25
- #define NPCM7XX_RESET_ADC 27
- #define NPCM7XX_RESET_SMB6 28
- #define NPCM7XX_RESET_SMB7 29
- #define NPCM7XX_RESET_SMB0 30
- #define NPCM7XX_RESET_SMB1 31
- /* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */
- #define NPCM7XX_RESET_MFT0 0
- #define NPCM7XX_RESET_MFT1 1
- #define NPCM7XX_RESET_MFT2 2
- #define NPCM7XX_RESET_MFT3 3
- #define NPCM7XX_RESET_MFT4 4
- #define NPCM7XX_RESET_MFT5 5
- #define NPCM7XX_RESET_MFT6 6
- #define NPCM7XX_RESET_MFT7 7
- #define NPCM7XX_RESET_MMC 8
- #define NPCM7XX_RESET_SDHC 9
- #define NPCM7XX_RESET_GFX_SYS 10
- #define NPCM7XX_RESET_AHB_PCIBRG 11
- #define NPCM7XX_RESET_VDMA 12
- #define NPCM7XX_RESET_ECE 13
- #define NPCM7XX_RESET_VCD 14
- #define NPCM7XX_RESET_OTP 16
- #define NPCM7XX_RESET_SIOX1 18
- #define NPCM7XX_RESET_SIOX2 19
- #define NPCM7XX_RESET_3DES 21
- #define NPCM7XX_RESET_PSPI1 22
- #define NPCM7XX_RESET_PSPI2 23
- #define NPCM7XX_RESET_GMAC2 25
- #define NPCM7XX_RESET_USB_HOST 26
- #define NPCM7XX_RESET_GMAC1 28
- #define NPCM7XX_RESET_CP 31
- /* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */
- #define NPCM7XX_RESET_PWM_M1 0
- #define NPCM7XX_RESET_SMB12 1
- #define NPCM7XX_RESET_SPIX 2
- #define NPCM7XX_RESET_SMB13 3
- #define NPCM7XX_RESET_UDC0 4
- #define NPCM7XX_RESET_UDC7 5
- #define NPCM7XX_RESET_UDC8 6
- #define NPCM7XX_RESET_UDC9 7
- #define NPCM7XX_RESET_PCI_MAILBOX 9
- #define NPCM7XX_RESET_SMB14 12
- #define NPCM7XX_RESET_SHA 13
- #define NPCM7XX_RESET_SEC_ECC 14
- #define NPCM7XX_RESET_PCIE_RC 15
- #define NPCM7XX_RESET_TIMER_10_14 16
- #define NPCM7XX_RESET_RNG 17
- #define NPCM7XX_RESET_SMB15 18
- #define NPCM7XX_RESET_SMB8 19
- #define NPCM7XX_RESET_SMB9 20
- #define NPCM7XX_RESET_SMB10 21
- #define NPCM7XX_RESET_SMB11 22
- #define NPCM7XX_RESET_ESPI 23
- #define NPCM7XX_RESET_USB_PHY_1 24
- #define NPCM7XX_RESET_USB_PHY_2 25
- #endif
|