mt8173-resets.h 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: Flora Fu, MediaTek
  5. */
  6. #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173
  7. #define _DT_BINDINGS_RESET_CONTROLLER_MT8173
  8. /* INFRACFG resets */
  9. #define MT8173_INFRA_EMI_REG_RST 0
  10. #define MT8173_INFRA_DRAMC0_A0_RST 1
  11. #define MT8173_INFRA_APCIRQ_EINT_RST 3
  12. #define MT8173_INFRA_APXGPT_RST 4
  13. #define MT8173_INFRA_SCPSYS_RST 5
  14. #define MT8173_INFRA_KP_RST 6
  15. #define MT8173_INFRA_PMIC_WRAP_RST 7
  16. #define MT8173_INFRA_MPIP_RST 8
  17. #define MT8173_INFRA_CEC_RST 9
  18. #define MT8173_INFRA_EMI_RST 32
  19. #define MT8173_INFRA_DRAMC0_RST 34
  20. #define MT8173_INFRA_APMIXEDSYS_RST 35
  21. #define MT8173_INFRA_MIPI_DSI_RST 36
  22. #define MT8173_INFRA_TRNG_RST 37
  23. #define MT8173_INFRA_SYSIRQ_RST 38
  24. #define MT8173_INFRA_MIPI_CSI_RST 39
  25. #define MT8173_INFRA_GCE_FAXI_RST 40
  26. #define MT8173_INFRA_MMIOMMURST 47
  27. /* PERICFG resets */
  28. #define MT8173_PERI_UART0_SW_RST 0
  29. #define MT8173_PERI_UART1_SW_RST 1
  30. #define MT8173_PERI_UART2_SW_RST 2
  31. #define MT8173_PERI_UART3_SW_RST 3
  32. #define MT8173_PERI_IRRX_SW_RST 4
  33. #define MT8173_PERI_PWM_SW_RST 8
  34. #define MT8173_PERI_AUXADC_SW_RST 10
  35. #define MT8173_PERI_DMA_SW_RST 11
  36. #define MT8173_PERI_I2C6_SW_RST 13
  37. #define MT8173_PERI_NFI_SW_RST 14
  38. #define MT8173_PERI_THERM_SW_RST 16
  39. #define MT8173_PERI_MSDC2_SW_RST 17
  40. #define MT8173_PERI_MSDC3_SW_RST 18
  41. #define MT8173_PERI_MSDC0_SW_RST 19
  42. #define MT8173_PERI_MSDC1_SW_RST 20
  43. #define MT8173_PERI_I2C0_SW_RST 22
  44. #define MT8173_PERI_I2C1_SW_RST 23
  45. #define MT8173_PERI_I2C2_SW_RST 24
  46. #define MT8173_PERI_I2C3_SW_RST 25
  47. #define MT8173_PERI_I2C4_SW_RST 26
  48. #define MT8173_PERI_HDMI_SW_RST 29
  49. #define MT8173_PERI_SPI0_SW_RST 33
  50. #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */