mt7629-resets.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2019 MediaTek Inc.
  4. */
  5. #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
  6. #define _DT_BINDINGS_RESET_CONTROLLER_MT7629
  7. /* INFRACFG resets */
  8. #define MT7629_INFRA_EMI_MPU_RST 0
  9. #define MT7629_INFRA_UART5_RST 2
  10. #define MT7629_INFRA_CIRQ_EINT_RST 3
  11. #define MT7629_INFRA_APXGPT_RST 4
  12. #define MT7629_INFRA_SCPSYS_RST 5
  13. #define MT7629_INFRA_KP_RST 6
  14. #define MT7629_INFRA_SPI1_RST 7
  15. #define MT7629_INFRA_SPI4_RST 8
  16. #define MT7629_INFRA_SYSTIMER_RST 9
  17. #define MT7629_INFRA_IRRX_RST 10
  18. #define MT7629_INFRA_AO_BUS_RST 16
  19. #define MT7629_INFRA_EMI_RST 32
  20. #define MT7629_INFRA_APMIXED_RST 35
  21. #define MT7629_INFRA_MIPI_RST 36
  22. #define MT7629_INFRA_TRNG_RST 37
  23. #define MT7629_INFRA_SYSCIRQ_RST 38
  24. #define MT7629_INFRA_MIPI_CSI_RST 39
  25. #define MT7629_INFRA_GCE_FAXI_RST 40
  26. #define MT7629_INFRA_I2C_SRAM_RST 41
  27. #define MT7629_INFRA_IOMMU_RST 47
  28. /* PERICFG resets */
  29. #define MT7629_PERI_UART0_SW_RST 0
  30. #define MT7629_PERI_UART1_SW_RST 1
  31. #define MT7629_PERI_UART2_SW_RST 2
  32. #define MT7629_PERI_BTIF_SW_RST 6
  33. #define MT7629_PERI_PWN_SW_RST 8
  34. #define MT7629_PERI_DMA_SW_RST 11
  35. #define MT7629_PERI_NFI_SW_RST 14
  36. #define MT7629_PERI_I2C0_SW_RST 22
  37. #define MT7629_PERI_SPI0_SW_RST 33
  38. #define MT7629_PERI_SPI1_SW_RST 34
  39. #define MT7629_PERI_FLASHIF_SW_RST 36
  40. /* PCIe Subsystem resets */
  41. #define MT7629_PCIE1_CORE_RST 19
  42. #define MT7629_PCIE1_MMIO_RST 20
  43. #define MT7629_PCIE1_HRST 21
  44. #define MT7629_PCIE1_USER_RST 22
  45. #define MT7629_PCIE1_PIPE_RST 23
  46. #define MT7629_PCIE0_CORE_RST 27
  47. #define MT7629_PCIE0_MMIO_RST 28
  48. #define MT7629_PCIE0_HRST 29
  49. #define MT7629_PCIE0_USER_RST 30
  50. #define MT7629_PCIE0_PIPE_RST 31
  51. /* SSUSB Subsystem resets */
  52. #define MT7629_SSUSB_PHY_PWR_RST 3
  53. #define MT7629_SSUSB_MAC_PWR_RST 4
  54. /* ETH Subsystem resets */
  55. #define MT7629_ETHSYS_SYS_RST 0
  56. #define MT7629_ETHSYS_MCM_RST 2
  57. #define MT7629_ETHSYS_HSDMA_RST 5
  58. #define MT7629_ETHSYS_FE_RST 6
  59. #define MT7629_ETHSYS_ESW_RST 16
  60. #define MT7629_ETHSYS_GMAC_RST 23
  61. #define MT7629_ETHSYS_EPHY_RST 24
  62. #define MT7629_ETHSYS_CRYPTO_RST 29
  63. #define MT7629_ETHSYS_PPE_RST 31
  64. #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */