amlogic,meson8b-reset.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2. /*
  3. * Copyright (c) 2016 BayLibre, SAS.
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
  7. #define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
  8. /* RESET0 */
  9. #define RESET_HIU 0
  10. #define RESET_VLD 1
  11. #define RESET_IQIDCT 2
  12. #define RESET_MC 3
  13. /* 8 */
  14. #define RESET_VIU 5
  15. #define RESET_AIU 6
  16. #define RESET_MCPU 7
  17. #define RESET_CCPU 8
  18. #define RESET_PMUX 9
  19. #define RESET_VENC 10
  20. #define RESET_ASSIST 11
  21. #define RESET_AFIFO2 12
  22. #define RESET_MDEC 13
  23. #define RESET_VLD_PART 14
  24. #define RESET_VIFIFO 15
  25. /* 16-31 */
  26. /* RESET1 */
  27. /* 32 */
  28. #define RESET_DEMUX 33
  29. #define RESET_USB_OTG 34
  30. #define RESET_DDR 35
  31. #define RESET_VDAC_1 36
  32. #define RESET_BT656 37
  33. #define RESET_AHB_SRAM 38
  34. #define RESET_AHB_BRIDGE 39
  35. #define RESET_PARSER 40
  36. #define RESET_BLKMV 41
  37. #define RESET_ISA 42
  38. #define RESET_ETHERNET 43
  39. #define RESET_ABUF 44
  40. #define RESET_AHB_DATA 45
  41. #define RESET_AHB_CNTL 46
  42. #define RESET_ROM_BOOT 47
  43. /* 48-63 */
  44. /* RESET2 */
  45. #define RESET_VD_RMEM 64
  46. #define RESET_AUDIN 65
  47. #define RESET_DBLK 66
  48. #define RESET_PIC_DC 67
  49. #define RESET_PSC 68
  50. #define RESET_NAND 69
  51. #define RESET_GE2D 70
  52. #define RESET_PARSER_REG 71
  53. #define RESET_PARSER_FETCH 72
  54. #define RESET_PARSER_CTL 73
  55. #define RESET_PARSER_TOP 74
  56. #define RESET_HDMI_APB 75
  57. #define RESET_AUDIO_APB 76
  58. #define RESET_MEDIA_CPU 77
  59. #define RESET_MALI 78
  60. #define RESET_HDMI_SYSTEM_RESET 79
  61. /* 80-95 */
  62. /* RESET3 */
  63. #define RESET_RING_OSCILLATOR 96
  64. #define RESET_SYS_CPU_0 97
  65. #define RESET_EFUSE 98
  66. #define RESET_SYS_CPU_BVCI 99
  67. #define RESET_AIFIFO 100
  68. #define RESET_AUDIO_PLL_MODULATOR 101
  69. #define RESET_AHB_BRIDGE_CNTL 102
  70. #define RESET_SYS_CPU_1 103
  71. #define RESET_AUDIO_DAC 104
  72. #define RESET_DEMUX_TOP 105
  73. #define RESET_DEMUX_DES 106
  74. #define RESET_DEMUX_S2P_0 107
  75. #define RESET_DEMUX_S2P_1 108
  76. #define RESET_DEMUX_RESET_0 109
  77. #define RESET_DEMUX_RESET_1 110
  78. #define RESET_DEMUX_RESET_2 111
  79. /* 112-127 */
  80. /* RESET4 */
  81. #define RESET_PL310 128
  82. #define RESET_A5_APB 129
  83. #define RESET_A5_AXI 130
  84. #define RESET_A5 131
  85. #define RESET_DVIN 132
  86. #define RESET_RDMA 133
  87. #define RESET_VENCI 134
  88. #define RESET_VENCP 135
  89. #define RESET_VENCT 136
  90. #define RESET_VDAC_4 137
  91. #define RESET_RTC 138
  92. #define RESET_A5_DEBUG 139
  93. #define RESET_VDI6 140
  94. #define RESET_VENCL 141
  95. /* 142-159 */
  96. /* RESET5 */
  97. #define RESET_DDR_PLL 160
  98. #define RESET_MISC_PLL 161
  99. #define RESET_SYS_PLL 162
  100. #define RESET_HPLL_PLL 163
  101. #define RESET_AUDIO_PLL 164
  102. #define RESET_VID2_PLL 165
  103. /* 166-191 */
  104. /* RESET6 */
  105. #define RESET_PERIPHS_GENERAL 192
  106. #define RESET_PERIPHS_IR_REMOTE 193
  107. #define RESET_PERIPHS_SMART_CARD 194
  108. #define RESET_PERIPHS_SAR_ADC 195
  109. #define RESET_PERIPHS_I2C_MASTER_0 196
  110. #define RESET_PERIPHS_I2C_MASTER_1 197
  111. #define RESET_PERIPHS_I2C_SLAVE 198
  112. #define RESET_PERIPHS_STREAM_INTERFACE 199
  113. #define RESET_PERIPHS_SDIO 200
  114. #define RESET_PERIPHS_UART_0 201
  115. #define RESET_PERIPHS_UART_1 202
  116. #define RESET_PERIPHS_ASYNC_0 203
  117. #define RESET_PERIPHS_ASYNC_1 204
  118. #define RESET_PERIPHS_SPI_0 205
  119. #define RESET_PERIPHS_SPI_1 206
  120. #define RESET_PERIPHS_LED_PWM 207
  121. /* 208-223 */
  122. /* RESET7 */
  123. /* 224-255 */
  124. #endif