altr,rst-mgr-a10.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
  4. */
  5. #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
  6. #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
  7. /* MPUMODRST */
  8. #define CPU0_RESET 0
  9. #define CPU1_RESET 1
  10. #define WDS_RESET 2
  11. #define SCUPER_RESET 3
  12. /* PER0MODRST */
  13. #define EMAC0_RESET 32
  14. #define EMAC1_RESET 33
  15. #define EMAC2_RESET 34
  16. #define USB0_RESET 35
  17. #define USB1_RESET 36
  18. #define NAND_RESET 37
  19. #define QSPI_RESET 38
  20. #define SDMMC_RESET 39
  21. #define EMAC0_OCP_RESET 40
  22. #define EMAC1_OCP_RESET 41
  23. #define EMAC2_OCP_RESET 42
  24. #define USB0_OCP_RESET 43
  25. #define USB1_OCP_RESET 44
  26. #define NAND_OCP_RESET 45
  27. #define QSPI_OCP_RESET 46
  28. #define SDMMC_OCP_RESET 47
  29. #define DMA_RESET 48
  30. #define SPIM0_RESET 49
  31. #define SPIM1_RESET 50
  32. #define SPIS0_RESET 51
  33. #define SPIS1_RESET 52
  34. #define DMA_OCP_RESET 53
  35. #define EMAC_PTP_RESET 54
  36. /* 55 is empty*/
  37. #define DMAIF0_RESET 56
  38. #define DMAIF1_RESET 57
  39. #define DMAIF2_RESET 58
  40. #define DMAIF3_RESET 59
  41. #define DMAIF4_RESET 60
  42. #define DMAIF5_RESET 61
  43. #define DMAIF6_RESET 62
  44. #define DMAIF7_RESET 63
  45. /* PER1MODRST */
  46. #define L4WD0_RESET 64
  47. #define L4WD1_RESET 65
  48. #define L4SYSTIMER0_RESET 66
  49. #define L4SYSTIMER1_RESET 67
  50. #define SPTIMER0_RESET 68
  51. #define SPTIMER1_RESET 69
  52. /* 70-71 is reserved */
  53. #define I2C0_RESET 72
  54. #define I2C1_RESET 73
  55. #define I2C2_RESET 74
  56. #define I2C3_RESET 75
  57. #define I2C4_RESET 76
  58. /* 77-79 is reserved */
  59. #define UART0_RESET 80
  60. #define UART1_RESET 81
  61. /* 82-87 is reserved */
  62. #define GPIO0_RESET 88
  63. #define GPIO1_RESET 89
  64. #define GPIO2_RESET 90
  65. /* BRGMODRST */
  66. #define HPS2FPGA_RESET 96
  67. #define LWHPS2FPGA_RESET 97
  68. #define FPGA2HPS_RESET 98
  69. #define F2SSDRAM0_RESET 99
  70. #define F2SSDRAM1_RESET 100
  71. #define F2SSDRAM2_RESET 101
  72. #define DDRSCH_RESET 102
  73. /* SYSMODRST*/
  74. #define ROM_RESET 128
  75. #define OCRAM_RESET 129
  76. /* 130 is reserved */
  77. #define FPGAMGR_RESET 131
  78. #define S2F_RESET 132
  79. #define SYSDBG_RESET 133
  80. #define OCRAM_OCP_RESET 134
  81. /* COLDMODRST */
  82. #define CLKMGRCOLD_RESET 160
  83. /* 161-162 is reserved */
  84. #define S2FCOLD_RESET 163
  85. #define TIMESTAMPCOLD_RESET 164
  86. #define TAPCOLD_RESET 165
  87. #define HMCCOLD_RESET 166
  88. #define IOMGRCOLD_RESET 167
  89. /* NRSTMODRST */
  90. #define NRSTPINOE_RESET 192
  91. /* DBGMODRST */
  92. #define DBG_RESET 224
  93. #endif