rzn1-pinctrl.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Defines macros and constants for Renesas RZ/N1 pin controller pin
  4. * muxing functions.
  5. */
  6. #ifndef __DT_BINDINGS_RZN1_PINCTRL_H
  7. #define __DT_BINDINGS_RZN1_PINCTRL_H
  8. #define RZN1_PINMUX(_gpio, _func) \
  9. (((_func) << 8) | (_gpio))
  10. /*
  11. * Given the different levels of muxing on the SoC, it was decided to
  12. * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO
  13. * muxes are all represented by one single value.
  14. *
  15. * You can derive the hardware value pretty easily too, as
  16. * 0...9 are Level 1
  17. * 10...71 are Level 2. The Level 2 mux will be set to this
  18. * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be
  19. * set accordingly.
  20. * 72...103 are for the 2 MDIO muxes.
  21. */
  22. #define RZN1_FUNC_HIGHZ 0
  23. #define RZN1_FUNC_0L 1
  24. #define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2
  25. #define RZN1_FUNC_CLK_ETH_NAND 3
  26. #define RZN1_FUNC_QSPI 4
  27. #define RZN1_FUNC_SDIO 5
  28. #define RZN1_FUNC_LCD 6
  29. #define RZN1_FUNC_LCD_E 7
  30. #define RZN1_FUNC_MSEBIM 8
  31. #define RZN1_FUNC_MSEBIS 9
  32. #define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */
  33. #define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0)
  34. #define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1)
  35. #define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2)
  36. #define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3)
  37. #define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4)
  38. #define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5)
  39. #define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6)
  40. #define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7)
  41. #define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8)
  42. #define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9)
  43. #define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10)
  44. #define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11)
  45. #define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12)
  46. #define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13)
  47. #define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14)
  48. #define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15)
  49. #define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16)
  50. #define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17)
  51. #define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18)
  52. #define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19)
  53. #define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20)
  54. #define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21)
  55. #define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22)
  56. #define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23)
  57. #define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24)
  58. #define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25)
  59. #define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26)
  60. #define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27)
  61. #define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28)
  62. #define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29)
  63. #define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30)
  64. #define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31)
  65. #define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32)
  66. #define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33)
  67. #define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34)
  68. #define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35)
  69. #define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36)
  70. #define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37)
  71. #define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38)
  72. #define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39)
  73. #define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40)
  74. #define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41)
  75. #define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42)
  76. #define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43)
  77. #define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44)
  78. #define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45)
  79. #define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46)
  80. #define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47)
  81. #define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48)
  82. #define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49)
  83. #define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50)
  84. #define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51)
  85. #define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52)
  86. #define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53)
  87. #define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54)
  88. #define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55)
  89. #define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56)
  90. #define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57)
  91. #define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58)
  92. #define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59)
  93. #define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60)
  94. #define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61)
  95. #define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62)
  96. /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */
  97. #define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0)
  98. #define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1)
  99. #define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2)
  100. #define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3)
  101. #define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4)
  102. #define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5)
  103. #define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6)
  104. #define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7)
  105. /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
  106. #define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8)
  107. #define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9)
  108. #define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10)
  109. #define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11)
  110. #define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12)
  111. #define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13)
  112. #define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14)
  113. #define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15)
  114. /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */
  115. #define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16)
  116. #define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17)
  117. #define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18)
  118. #define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19)
  119. #define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20)
  120. #define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21)
  121. #define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22)
  122. #define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23)
  123. /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
  124. #define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24)
  125. #define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25)
  126. #define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26)
  127. #define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27)
  128. #define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28)
  129. #define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29)
  130. #define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30)
  131. #define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31)
  132. #define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32)
  133. #endif /* __DT_BINDINGS_RZN1_PINCTRL_H */