ti-dp83869.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Device Tree constants for the Texas Instruments DP83869 PHY
  4. *
  5. * Author: Dan Murphy <dmurphy@ti.com>
  6. *
  7. * Copyright: (C) 2019 Texas Instruments, Inc.
  8. */
  9. #ifndef _DT_BINDINGS_TI_DP83869_H
  10. #define _DT_BINDINGS_TI_DP83869_H
  11. /* PHY CTRL bits */
  12. #define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
  13. #define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
  14. #define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
  15. #define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
  16. /* IO_MUX_CFG - Clock output selection */
  17. #define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0
  18. #define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1
  19. #define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2
  20. #define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3
  21. #define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
  22. #define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
  23. #define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
  24. #define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
  25. #define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8
  26. #define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9
  27. #define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa
  28. #define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb
  29. #define DP83869_CLK_O_SEL_REF_CLK 0xc
  30. #define DP83869_RGMII_COPPER_ETHERNET 0x00
  31. #define DP83869_RGMII_1000_BASE 0x01
  32. #define DP83869_RGMII_100_BASE 0x02
  33. #define DP83869_RGMII_SGMII_BRIDGE 0x03
  34. #define DP83869_1000M_MEDIA_CONVERT 0x04
  35. #define DP83869_100M_MEDIA_CONVERT 0x05
  36. #define DP83869_SGMII_COPPER_ETHERNET 0x06
  37. #endif