zx296718-clock.h 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2015 - 2016 ZTE Corporation.
  4. */
  5. #ifndef __DT_BINDINGS_CLOCK_ZX296718_H
  6. #define __DT_BINDINGS_CLOCK_ZX296718_H
  7. /* PLL */
  8. #define ZX296718_PLL_CPU 1
  9. #define ZX296718_PLL_MAC 2
  10. #define ZX296718_PLL_MM0 3
  11. #define ZX296718_PLL_MM1 4
  12. #define ZX296718_PLL_VGA 5
  13. #define ZX296718_PLL_DDR 6
  14. #define ZX296718_PLL_AUDIO 7
  15. #define ZX296718_PLL_HSIC 8
  16. #define CPU_DBG_GATE 9
  17. #define A72_GATE 10
  18. #define CPU_PERI_GATE 11
  19. #define A53_GATE 12
  20. #define DDR1_GATE 13
  21. #define DDR0_GATE 14
  22. #define SD1_WCLK 15
  23. #define SD1_AHB 16
  24. #define SD0_WCLK 17
  25. #define SD0_AHB 18
  26. #define EMMC_WCLK 19
  27. #define EMMC_NAND_AXI 20
  28. #define NAND_WCLK 21
  29. #define EMMC_NAND_AHB 22
  30. #define LSP1_148M5 23
  31. #define LSP1_99M 24
  32. #define LSP1_24M 25
  33. #define LSP0_74M25 26
  34. #define LSP0_32K 27
  35. #define LSP0_148M5 28
  36. #define LSP0_99M 29
  37. #define LSP0_24M 30
  38. #define DEMUX_AXI 31
  39. #define DEMUX_APB 32
  40. #define DEMUX_148M5 33
  41. #define DEMUX_108M 34
  42. #define AUDIO_APB 35
  43. #define AUDIO_99M 36
  44. #define AUDIO_24M 37
  45. #define AUDIO_16M384 38
  46. #define AUDIO_32K 39
  47. #define WDT_WCLK 40
  48. #define TIMER_WCLK 41
  49. #define VDE_ACLK 42
  50. #define VCE_ACLK 43
  51. #define HDE_ACLK 44
  52. #define GPU_ACLK 45
  53. #define SAPPU_ACLK 46
  54. #define SAPPU_WCLK 47
  55. #define VOU_ACLK 48
  56. #define VOU_MAIN_WCLK 49
  57. #define VOU_AUX_WCLK 50
  58. #define VOU_PPU_WCLK 51
  59. #define MIPI_CFG_CLK 52
  60. #define VGA_I2C_WCLK 53
  61. #define MIPI_REF_CLK 54
  62. #define HDMI_OSC_CEC 55
  63. #define HDMI_OSC_CLK 56
  64. #define HDMI_XCLK 57
  65. #define VIU_M0_ACLK 58
  66. #define VIU_M1_ACLK 59
  67. #define VIU_WCLK 60
  68. #define VIU_JPEG_WCLK 61
  69. #define VIU_CFG_CLK 62
  70. #define TS_SYS_WCLK 63
  71. #define TS_SYS_108M 64
  72. #define USB20_HCLK 65
  73. #define USB20_PHY_CLK 66
  74. #define USB21_HCLK 67
  75. #define USB21_PHY_CLK 68
  76. #define GMAC_RMIICLK 69
  77. #define GMAC_PCLK 70
  78. #define GMAC_ACLK 71
  79. #define GMAC_RFCLK 72
  80. #define TEMPSENSOR_GATE 73
  81. #define TOP_NR_CLKS 74
  82. #define LSP0_TIMER3_PCLK 1
  83. #define LSP0_TIMER3_WCLK 2
  84. #define LSP0_TIMER4_PCLK 3
  85. #define LSP0_TIMER4_WCLK 4
  86. #define LSP0_TIMER5_PCLK 5
  87. #define LSP0_TIMER5_WCLK 6
  88. #define LSP0_UART3_PCLK 7
  89. #define LSP0_UART3_WCLK 8
  90. #define LSP0_UART1_PCLK 9
  91. #define LSP0_UART1_WCLK 10
  92. #define LSP0_UART2_PCLK 11
  93. #define LSP0_UART2_WCLK 12
  94. #define LSP0_SPIFC0_PCLK 13
  95. #define LSP0_SPIFC0_WCLK 14
  96. #define LSP0_I2C4_PCLK 15
  97. #define LSP0_I2C4_WCLK 16
  98. #define LSP0_I2C5_PCLK 17
  99. #define LSP0_I2C5_WCLK 18
  100. #define LSP0_SSP0_PCLK 19
  101. #define LSP0_SSP0_WCLK 20
  102. #define LSP0_SSP1_PCLK 21
  103. #define LSP0_SSP1_WCLK 22
  104. #define LSP0_USIM_PCLK 23
  105. #define LSP0_USIM_WCLK 24
  106. #define LSP0_GPIO_PCLK 25
  107. #define LSP0_GPIO_WCLK 26
  108. #define LSP0_I2C3_PCLK 27
  109. #define LSP0_I2C3_WCLK 28
  110. #define LSP0_NR_CLKS 29
  111. #define LSP1_UART4_PCLK 1
  112. #define LSP1_UART4_WCLK 2
  113. #define LSP1_UART5_PCLK 3
  114. #define LSP1_UART5_WCLK 4
  115. #define LSP1_PWM_PCLK 5
  116. #define LSP1_PWM_WCLK 6
  117. #define LSP1_I2C2_PCLK 7
  118. #define LSP1_I2C2_WCLK 8
  119. #define LSP1_SSP2_PCLK 9
  120. #define LSP1_SSP2_WCLK 10
  121. #define LSP1_SSP3_PCLK 11
  122. #define LSP1_SSP3_WCLK 12
  123. #define LSP1_SSP4_PCLK 13
  124. #define LSP1_SSP4_WCLK 14
  125. #define LSP1_USIM1_PCLK 15
  126. #define LSP1_USIM1_WCLK 16
  127. #define LSP1_NR_CLKS 17
  128. #define AUDIO_I2S0_WCLK 1
  129. #define AUDIO_I2S0_PCLK 2
  130. #define AUDIO_I2S1_WCLK 3
  131. #define AUDIO_I2S1_PCLK 4
  132. #define AUDIO_I2S2_WCLK 5
  133. #define AUDIO_I2S2_PCLK 6
  134. #define AUDIO_I2S3_WCLK 7
  135. #define AUDIO_I2S3_PCLK 8
  136. #define AUDIO_I2C0_WCLK 9
  137. #define AUDIO_I2C0_PCLK 10
  138. #define AUDIO_SPDIF0_WCLK 11
  139. #define AUDIO_SPDIF0_PCLK 12
  140. #define AUDIO_SPDIF1_WCLK 13
  141. #define AUDIO_SPDIF1_PCLK 14
  142. #define AUDIO_TIMER_WCLK 15
  143. #define AUDIO_TIMER_PCLK 16
  144. #define AUDIO_TDM_WCLK 17
  145. #define AUDIO_TDM_PCLK 18
  146. #define AUDIO_TS_PCLK 19
  147. #define I2S0_WCLK_MUX 20
  148. #define I2S1_WCLK_MUX 21
  149. #define I2S2_WCLK_MUX 22
  150. #define I2S3_WCLK_MUX 23
  151. #define AUDIO_NR_CLKS 24
  152. #endif