tegra210-car.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * This header provides constants for binding nvidia,tegra210-car.
  4. *
  5. * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
  6. * registers. These IDs often match those in the CAR's RST_DEVICES registers,
  7. * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
  8. * this case, those clocks are assigned IDs above 224 in order to highlight
  9. * this issue. Implementations that interpret these clock IDs as bit values
  10. * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  11. * explicitly handle these special cases.
  12. *
  13. * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
  14. * above.
  15. */
  16. #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
  17. #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
  18. /* 0 */
  19. /* 1 */
  20. /* 2 */
  21. #define TEGRA210_CLK_ISPB 3
  22. #define TEGRA210_CLK_RTC 4
  23. #define TEGRA210_CLK_TIMER 5
  24. #define TEGRA210_CLK_UARTA 6
  25. /* 7 (register bit affects uartb and vfir) */
  26. #define TEGRA210_CLK_GPIO 8
  27. #define TEGRA210_CLK_SDMMC2 9
  28. /* 10 (register bit affects spdif_in and spdif_out) */
  29. #define TEGRA210_CLK_I2S1 11
  30. #define TEGRA210_CLK_I2C1 12
  31. /* 13 */
  32. #define TEGRA210_CLK_SDMMC1 14
  33. #define TEGRA210_CLK_SDMMC4 15
  34. /* 16 */
  35. #define TEGRA210_CLK_PWM 17
  36. #define TEGRA210_CLK_I2S2 18
  37. /* 19 */
  38. /* 20 (register bit affects vi and vi_sensor) */
  39. /* 21 */
  40. #define TEGRA210_CLK_USBD 22
  41. #define TEGRA210_CLK_ISPA 23
  42. /* 24 */
  43. /* 25 */
  44. #define TEGRA210_CLK_DISP2 26
  45. #define TEGRA210_CLK_DISP1 27
  46. #define TEGRA210_CLK_HOST1X 28
  47. /* 29 */
  48. #define TEGRA210_CLK_I2S0 30
  49. /* 31 */
  50. #define TEGRA210_CLK_MC 32
  51. #define TEGRA210_CLK_AHBDMA 33
  52. #define TEGRA210_CLK_APBDMA 34
  53. /* 35 */
  54. /* 36 */
  55. /* 37 */
  56. #define TEGRA210_CLK_PMC 38
  57. /* 39 (register bit affects fuse and fuse_burn) */
  58. #define TEGRA210_CLK_KFUSE 40
  59. #define TEGRA210_CLK_SBC1 41
  60. /* 42 */
  61. /* 43 */
  62. #define TEGRA210_CLK_SBC2 44
  63. /* 45 */
  64. #define TEGRA210_CLK_SBC3 46
  65. #define TEGRA210_CLK_I2C5 47
  66. #define TEGRA210_CLK_DSIA 48
  67. /* 49 */
  68. /* 50 */
  69. /* 51 */
  70. #define TEGRA210_CLK_CSI 52
  71. /* 53 */
  72. #define TEGRA210_CLK_I2C2 54
  73. #define TEGRA210_CLK_UARTC 55
  74. #define TEGRA210_CLK_MIPI_CAL 56
  75. #define TEGRA210_CLK_EMC 57
  76. #define TEGRA210_CLK_USB2 58
  77. /* 59 */
  78. /* 60 */
  79. /* 61 */
  80. /* 62 */
  81. #define TEGRA210_CLK_BSEV 63
  82. /* 64 */
  83. #define TEGRA210_CLK_UARTD 65
  84. /* 66 */
  85. #define TEGRA210_CLK_I2C3 67
  86. #define TEGRA210_CLK_SBC4 68
  87. #define TEGRA210_CLK_SDMMC3 69
  88. #define TEGRA210_CLK_PCIE 70
  89. #define TEGRA210_CLK_OWR 71
  90. #define TEGRA210_CLK_AFI 72
  91. #define TEGRA210_CLK_CSITE 73
  92. /* 74 */
  93. /* 75 */
  94. #define TEGRA210_CLK_LA 76
  95. /* 77 */
  96. #define TEGRA210_CLK_SOC_THERM 78
  97. #define TEGRA210_CLK_DTV 79
  98. /* 80 */
  99. #define TEGRA210_CLK_I2CSLOW 81
  100. #define TEGRA210_CLK_DSIB 82
  101. #define TEGRA210_CLK_TSEC 83
  102. /* 84 */
  103. /* 85 */
  104. /* 86 */
  105. /* 87 */
  106. /* 88 */
  107. #define TEGRA210_CLK_XUSB_HOST 89
  108. /* 90 */
  109. /* 91 */
  110. #define TEGRA210_CLK_CSUS 92
  111. /* 93 */
  112. /* 94 */
  113. /* 95 (bit affects xusb_dev and xusb_dev_src) */
  114. /* 96 */
  115. /* 97 */
  116. /* 98 */
  117. #define TEGRA210_CLK_MSELECT 99
  118. #define TEGRA210_CLK_TSENSOR 100
  119. #define TEGRA210_CLK_I2S3 101
  120. #define TEGRA210_CLK_I2S4 102
  121. #define TEGRA210_CLK_I2C4 103
  122. /* 104 */
  123. /* 105 */
  124. #define TEGRA210_CLK_D_AUDIO 106
  125. #define TEGRA210_CLK_APB2APE 107
  126. /* 108 */
  127. /* 109 */
  128. /* 110 */
  129. #define TEGRA210_CLK_HDA2CODEC_2X 111
  130. /* 112 */
  131. /* 113 */
  132. /* 114 */
  133. /* 115 */
  134. /* 116 */
  135. /* 117 */
  136. #define TEGRA210_CLK_SPDIF_2X 118
  137. #define TEGRA210_CLK_ACTMON 119
  138. #define TEGRA210_CLK_EXTERN1 120
  139. #define TEGRA210_CLK_EXTERN2 121
  140. #define TEGRA210_CLK_EXTERN3 122
  141. #define TEGRA210_CLK_SATA_OOB 123
  142. #define TEGRA210_CLK_SATA 124
  143. #define TEGRA210_CLK_HDA 125
  144. /* 126 */
  145. /* 127 */
  146. #define TEGRA210_CLK_HDA2HDMI 128
  147. /* 129 */
  148. /* 130 */
  149. /* 131 */
  150. /* 132 */
  151. /* 133 */
  152. /* 134 */
  153. /* 135 */
  154. #define TEGRA210_CLK_CEC 136
  155. /* 137 */
  156. /* 138 */
  157. /* 139 */
  158. /* 140 */
  159. /* 141 */
  160. /* 142 */
  161. /* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
  162. #define TEGRA210_CLK_XUSB_GATE 143
  163. #define TEGRA210_CLK_CILAB 144
  164. #define TEGRA210_CLK_CILCD 145
  165. #define TEGRA210_CLK_CILE 146
  166. #define TEGRA210_CLK_DSIALP 147
  167. #define TEGRA210_CLK_DSIBLP 148
  168. #define TEGRA210_CLK_ENTROPY 149
  169. /* 150 */
  170. /* 151 */
  171. #define TEGRA210_CLK_DP2 152
  172. /* 153 */
  173. /* 154 */
  174. /* 155 (bit affects dfll_ref and dfll_soc) */
  175. #define TEGRA210_CLK_XUSB_SS 156
  176. /* 157 */
  177. /* 158 */
  178. /* 159 */
  179. /* 160 */
  180. #define TEGRA210_CLK_DMIC1 161
  181. #define TEGRA210_CLK_DMIC2 162
  182. /* 163 */
  183. /* 164 */
  184. /* 165 */
  185. #define TEGRA210_CLK_I2C6 166
  186. /* 167 */
  187. /* 168 */
  188. /* 169 */
  189. /* 170 */
  190. #define TEGRA210_CLK_VIM2_CLK 171
  191. /* 172 */
  192. #define TEGRA210_CLK_MIPIBIF 173
  193. /* 174 */
  194. /* 175 */
  195. /* 176 */
  196. #define TEGRA210_CLK_CLK72MHZ 177
  197. #define TEGRA210_CLK_VIC03 178
  198. /* 179 */
  199. /* 180 */
  200. #define TEGRA210_CLK_DPAUX 181
  201. #define TEGRA210_CLK_SOR0 182
  202. #define TEGRA210_CLK_SOR1 183
  203. #define TEGRA210_CLK_GPU 184
  204. #define TEGRA210_CLK_DBGAPB 185
  205. /* 186 */
  206. #define TEGRA210_CLK_PLL_P_OUT_ADSP 187
  207. /* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/
  208. #define TEGRA210_CLK_PLL_G_REF 189
  209. /* 190 */
  210. /* 191 */
  211. /* 192 */
  212. #define TEGRA210_CLK_SDMMC_LEGACY 193
  213. #define TEGRA210_CLK_NVDEC 194
  214. #define TEGRA210_CLK_NVJPG 195
  215. /* 196 */
  216. #define TEGRA210_CLK_DMIC3 197
  217. #define TEGRA210_CLK_APE 198
  218. #define TEGRA210_CLK_ADSP 199
  219. /* 200 */
  220. /* 201 */
  221. #define TEGRA210_CLK_MAUD 202
  222. /* 203 */
  223. /* 204 */
  224. /* 205 */
  225. #define TEGRA210_CLK_TSECB 206
  226. #define TEGRA210_CLK_DPAUX1 207
  227. #define TEGRA210_CLK_VI_I2C 208
  228. #define TEGRA210_CLK_HSIC_TRK 209
  229. #define TEGRA210_CLK_USB2_TRK 210
  230. #define TEGRA210_CLK_QSPI 211
  231. #define TEGRA210_CLK_UARTAPE 212
  232. /* 213 */
  233. /* 214 */
  234. /* 215 */
  235. /* 216 */
  236. /* 217 */
  237. #define TEGRA210_CLK_ADSP_NEON 218
  238. #define TEGRA210_CLK_NVENC 219
  239. #define TEGRA210_CLK_IQC2 220
  240. #define TEGRA210_CLK_IQC1 221
  241. #define TEGRA210_CLK_SOR_SAFE 222
  242. #define TEGRA210_CLK_PLL_P_OUT_CPU 223
  243. #define TEGRA210_CLK_UARTB 224
  244. #define TEGRA210_CLK_VFIR 225
  245. #define TEGRA210_CLK_SPDIF_IN 226
  246. #define TEGRA210_CLK_SPDIF_OUT 227
  247. #define TEGRA210_CLK_VI 228
  248. #define TEGRA210_CLK_VI_SENSOR 229
  249. #define TEGRA210_CLK_FUSE 230
  250. #define TEGRA210_CLK_FUSE_BURN 231
  251. #define TEGRA210_CLK_CLK_32K 232
  252. #define TEGRA210_CLK_CLK_M 233
  253. #define TEGRA210_CLK_CLK_M_DIV2 234
  254. #define TEGRA210_CLK_CLK_M_DIV4 235
  255. #define TEGRA210_CLK_OSC_DIV2 234
  256. #define TEGRA210_CLK_OSC_DIV4 235
  257. #define TEGRA210_CLK_PLL_REF 236
  258. #define TEGRA210_CLK_PLL_C 237
  259. #define TEGRA210_CLK_PLL_C_OUT1 238
  260. #define TEGRA210_CLK_PLL_C2 239
  261. #define TEGRA210_CLK_PLL_C3 240
  262. #define TEGRA210_CLK_PLL_M 241
  263. #define TEGRA210_CLK_PLL_M_OUT1 242
  264. #define TEGRA210_CLK_PLL_P 243
  265. #define TEGRA210_CLK_PLL_P_OUT1 244
  266. #define TEGRA210_CLK_PLL_P_OUT2 245
  267. #define TEGRA210_CLK_PLL_P_OUT3 246
  268. #define TEGRA210_CLK_PLL_P_OUT4 247
  269. #define TEGRA210_CLK_PLL_A 248
  270. #define TEGRA210_CLK_PLL_A_OUT0 249
  271. #define TEGRA210_CLK_PLL_D 250
  272. #define TEGRA210_CLK_PLL_D_OUT0 251
  273. #define TEGRA210_CLK_PLL_D2 252
  274. #define TEGRA210_CLK_PLL_D2_OUT0 253
  275. #define TEGRA210_CLK_PLL_U 254
  276. #define TEGRA210_CLK_PLL_U_480M 255
  277. #define TEGRA210_CLK_PLL_U_60M 256
  278. #define TEGRA210_CLK_PLL_U_48M 257
  279. /* 258 */
  280. #define TEGRA210_CLK_PLL_X 259
  281. #define TEGRA210_CLK_PLL_X_OUT0 260
  282. #define TEGRA210_CLK_PLL_RE_VCO 261
  283. #define TEGRA210_CLK_PLL_RE_OUT 262
  284. #define TEGRA210_CLK_PLL_E 263
  285. #define TEGRA210_CLK_SPDIF_IN_SYNC 264
  286. #define TEGRA210_CLK_I2S0_SYNC 265
  287. #define TEGRA210_CLK_I2S1_SYNC 266
  288. #define TEGRA210_CLK_I2S2_SYNC 267
  289. #define TEGRA210_CLK_I2S3_SYNC 268
  290. #define TEGRA210_CLK_I2S4_SYNC 269
  291. #define TEGRA210_CLK_VIMCLK_SYNC 270
  292. #define TEGRA210_CLK_AUDIO0 271
  293. #define TEGRA210_CLK_AUDIO1 272
  294. #define TEGRA210_CLK_AUDIO2 273
  295. #define TEGRA210_CLK_AUDIO3 274
  296. #define TEGRA210_CLK_AUDIO4 275
  297. #define TEGRA210_CLK_SPDIF 276
  298. /* 277 */
  299. /* 278 */
  300. /* 279 */
  301. /* 280 */
  302. #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
  303. #define TEGRA210_CLK_SOR0_OUT 281
  304. #define TEGRA210_CLK_SOR1_OUT 282
  305. /* 283 */
  306. #define TEGRA210_CLK_XUSB_HOST_SRC 284
  307. #define TEGRA210_CLK_XUSB_FALCON_SRC 285
  308. #define TEGRA210_CLK_XUSB_FS_SRC 286
  309. #define TEGRA210_CLK_XUSB_SS_SRC 287
  310. #define TEGRA210_CLK_XUSB_DEV_SRC 288
  311. #define TEGRA210_CLK_XUSB_DEV 289
  312. #define TEGRA210_CLK_XUSB_HS_SRC 290
  313. #define TEGRA210_CLK_SCLK 291
  314. #define TEGRA210_CLK_HCLK 292
  315. #define TEGRA210_CLK_PCLK 293
  316. #define TEGRA210_CLK_CCLK_G 294
  317. #define TEGRA210_CLK_CCLK_LP 295
  318. #define TEGRA210_CLK_DFLL_REF 296
  319. #define TEGRA210_CLK_DFLL_SOC 297
  320. #define TEGRA210_CLK_VI_SENSOR2 298
  321. #define TEGRA210_CLK_PLL_P_OUT5 299
  322. #define TEGRA210_CLK_CML0 300
  323. #define TEGRA210_CLK_CML1 301
  324. #define TEGRA210_CLK_PLL_C4 302
  325. #define TEGRA210_CLK_PLL_DP 303
  326. #define TEGRA210_CLK_PLL_E_MUX 304
  327. #define TEGRA210_CLK_PLL_MB 305
  328. #define TEGRA210_CLK_PLL_A1 306
  329. #define TEGRA210_CLK_PLL_D_DSI_OUT 307
  330. #define TEGRA210_CLK_PLL_C4_OUT0 308
  331. #define TEGRA210_CLK_PLL_C4_OUT1 309
  332. #define TEGRA210_CLK_PLL_C4_OUT2 310
  333. #define TEGRA210_CLK_PLL_C4_OUT3 311
  334. #define TEGRA210_CLK_PLL_U_OUT 312
  335. #define TEGRA210_CLK_PLL_U_OUT1 313
  336. #define TEGRA210_CLK_PLL_U_OUT2 314
  337. #define TEGRA210_CLK_USB2_HSIC_TRK 315
  338. #define TEGRA210_CLK_PLL_P_OUT_HSIO 316
  339. #define TEGRA210_CLK_PLL_P_OUT_XUSB 317
  340. #define TEGRA210_CLK_XUSB_SSP_SRC 318
  341. #define TEGRA210_CLK_PLL_RE_OUT1 319
  342. #define TEGRA210_CLK_PLL_MB_UD 320
  343. #define TEGRA210_CLK_PLL_P_UD 321
  344. #define TEGRA210_CLK_ISP 322
  345. #define TEGRA210_CLK_PLL_A_OUT_ADSP 323
  346. #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
  347. /* 325 */
  348. #define TEGRA210_CLK_OSC 326
  349. #define TEGRA210_CLK_CSI_TPG 327
  350. /* 328 */
  351. /* 329 */
  352. /* 330 */
  353. /* 331 */
  354. /* 332 */
  355. /* 333 */
  356. /* 334 */
  357. /* 335 */
  358. /* 336 */
  359. /* 337 */
  360. /* 338 */
  361. /* 339 */
  362. /* 340 */
  363. /* 341 */
  364. /* 342 */
  365. /* 343 */
  366. /* 344 */
  367. /* 345 */
  368. /* 346 */
  369. /* 347 */
  370. /* 348 */
  371. /* 349 */
  372. #define TEGRA210_CLK_AUDIO0_MUX 350
  373. #define TEGRA210_CLK_AUDIO1_MUX 351
  374. #define TEGRA210_CLK_AUDIO2_MUX 352
  375. #define TEGRA210_CLK_AUDIO3_MUX 353
  376. #define TEGRA210_CLK_AUDIO4_MUX 354
  377. #define TEGRA210_CLK_SPDIF_MUX 355
  378. /* 356 */
  379. /* 357 */
  380. /* 358 */
  381. #define TEGRA210_CLK_DSIA_MUX 359
  382. #define TEGRA210_CLK_DSIB_MUX 360
  383. /* 361 */
  384. #define TEGRA210_CLK_XUSB_SS_DIV2 362
  385. #define TEGRA210_CLK_PLL_M_UD 363
  386. #define TEGRA210_CLK_PLL_C_UD 364
  387. #define TEGRA210_CLK_SCLK_MUX 365
  388. #define TEGRA210_CLK_ACLK 370
  389. #define TEGRA210_CLK_DMIC1_SYNC_CLK 388
  390. #define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
  391. #define TEGRA210_CLK_DMIC2_SYNC_CLK 390
  392. #define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391
  393. #define TEGRA210_CLK_DMIC3_SYNC_CLK 392
  394. #define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393
  395. #define TEGRA210_CLK_CLK_MAX 394
  396. #endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */