tegra20-car.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * This header provides constants for binding nvidia,tegra20-car.
  4. *
  5. * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
  6. * registers. These IDs often match those in the CAR's RST_DEVICES registers,
  7. * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
  8. * this case, those clocks are assigned IDs above 95 in order to highlight
  9. * this issue. Implementations that interpret these clock IDs as bit values
  10. * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  11. * explicitly handle these special cases.
  12. *
  13. * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
  14. * above.
  15. */
  16. #ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
  17. #define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
  18. #define TEGRA20_CLK_CPU 0
  19. /* 1 */
  20. /* 2 */
  21. #define TEGRA20_CLK_AC97 3
  22. #define TEGRA20_CLK_RTC 4
  23. #define TEGRA20_CLK_TIMER 5
  24. #define TEGRA20_CLK_UARTA 6
  25. /* 7 (register bit affects uart2 and vfir) */
  26. #define TEGRA20_CLK_GPIO 8
  27. #define TEGRA20_CLK_SDMMC2 9
  28. /* 10 (register bit affects spdif_in and spdif_out) */
  29. #define TEGRA20_CLK_I2S1 11
  30. #define TEGRA20_CLK_I2C1 12
  31. #define TEGRA20_CLK_NDFLASH 13
  32. #define TEGRA20_CLK_SDMMC1 14
  33. #define TEGRA20_CLK_SDMMC4 15
  34. #define TEGRA20_CLK_TWC 16
  35. #define TEGRA20_CLK_PWM 17
  36. #define TEGRA20_CLK_I2S2 18
  37. #define TEGRA20_CLK_EPP 19
  38. /* 20 (register bit affects vi and vi_sensor) */
  39. #define TEGRA20_CLK_GR2D 21
  40. #define TEGRA20_CLK_USBD 22
  41. #define TEGRA20_CLK_ISP 23
  42. #define TEGRA20_CLK_GR3D 24
  43. #define TEGRA20_CLK_IDE 25
  44. #define TEGRA20_CLK_DISP2 26
  45. #define TEGRA20_CLK_DISP1 27
  46. #define TEGRA20_CLK_HOST1X 28
  47. #define TEGRA20_CLK_VCP 29
  48. /* 30 */
  49. #define TEGRA20_CLK_CACHE2 31
  50. #define TEGRA20_CLK_MC 32
  51. #define TEGRA20_CLK_AHBDMA 33
  52. #define TEGRA20_CLK_APBDMA 34
  53. /* 35 */
  54. #define TEGRA20_CLK_KBC 36
  55. #define TEGRA20_CLK_STAT_MON 37
  56. #define TEGRA20_CLK_PMC 38
  57. #define TEGRA20_CLK_FUSE 39
  58. #define TEGRA20_CLK_KFUSE 40
  59. #define TEGRA20_CLK_SBC1 41
  60. #define TEGRA20_CLK_NOR 42
  61. #define TEGRA20_CLK_SPI 43
  62. #define TEGRA20_CLK_SBC2 44
  63. #define TEGRA20_CLK_XIO 45
  64. #define TEGRA20_CLK_SBC3 46
  65. #define TEGRA20_CLK_DVC 47
  66. #define TEGRA20_CLK_DSI 48
  67. /* 49 (register bit affects tvo and cve) */
  68. #define TEGRA20_CLK_MIPI 50
  69. #define TEGRA20_CLK_HDMI 51
  70. #define TEGRA20_CLK_CSI 52
  71. #define TEGRA20_CLK_TVDAC 53
  72. #define TEGRA20_CLK_I2C2 54
  73. #define TEGRA20_CLK_UARTC 55
  74. /* 56 */
  75. #define TEGRA20_CLK_EMC 57
  76. #define TEGRA20_CLK_USB2 58
  77. #define TEGRA20_CLK_USB3 59
  78. #define TEGRA20_CLK_MPE 60
  79. #define TEGRA20_CLK_VDE 61
  80. #define TEGRA20_CLK_BSEA 62
  81. #define TEGRA20_CLK_BSEV 63
  82. #define TEGRA20_CLK_SPEEDO 64
  83. #define TEGRA20_CLK_UARTD 65
  84. #define TEGRA20_CLK_UARTE 66
  85. #define TEGRA20_CLK_I2C3 67
  86. #define TEGRA20_CLK_SBC4 68
  87. #define TEGRA20_CLK_SDMMC3 69
  88. #define TEGRA20_CLK_PEX 70
  89. #define TEGRA20_CLK_OWR 71
  90. #define TEGRA20_CLK_AFI 72
  91. #define TEGRA20_CLK_CSITE 73
  92. /* 74 */
  93. #define TEGRA20_CLK_AVPUCQ 75
  94. #define TEGRA20_CLK_LA 76
  95. /* 77 */
  96. /* 78 */
  97. /* 79 */
  98. /* 80 */
  99. /* 81 */
  100. /* 82 */
  101. /* 83 */
  102. #define TEGRA20_CLK_IRAMA 84
  103. #define TEGRA20_CLK_IRAMB 85
  104. #define TEGRA20_CLK_IRAMC 86
  105. #define TEGRA20_CLK_IRAMD 87
  106. #define TEGRA20_CLK_CRAM2 88
  107. #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
  108. #define TEGRA20_CLK_CLK_D 90
  109. /* 91 */
  110. #define TEGRA20_CLK_CSUS 92
  111. #define TEGRA20_CLK_CDEV2 93
  112. #define TEGRA20_CLK_CDEV1 94
  113. /* 95 */
  114. #define TEGRA20_CLK_UARTB 96
  115. #define TEGRA20_CLK_VFIR 97
  116. #define TEGRA20_CLK_SPDIF_IN 98
  117. #define TEGRA20_CLK_SPDIF_OUT 99
  118. #define TEGRA20_CLK_VI 100
  119. #define TEGRA20_CLK_VI_SENSOR 101
  120. #define TEGRA20_CLK_TVO 102
  121. #define TEGRA20_CLK_CVE 103
  122. #define TEGRA20_CLK_OSC 104
  123. #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
  124. #define TEGRA20_CLK_CLK_M 106
  125. #define TEGRA20_CLK_SCLK 107
  126. #define TEGRA20_CLK_CCLK 108
  127. #define TEGRA20_CLK_HCLK 109
  128. #define TEGRA20_CLK_PCLK 110
  129. /* 111 */
  130. #define TEGRA20_CLK_PLL_A 112
  131. #define TEGRA20_CLK_PLL_A_OUT0 113
  132. #define TEGRA20_CLK_PLL_C 114
  133. #define TEGRA20_CLK_PLL_C_OUT1 115
  134. #define TEGRA20_CLK_PLL_D 116
  135. #define TEGRA20_CLK_PLL_D_OUT0 117
  136. #define TEGRA20_CLK_PLL_E 118
  137. #define TEGRA20_CLK_PLL_M 119
  138. #define TEGRA20_CLK_PLL_M_OUT1 120
  139. #define TEGRA20_CLK_PLL_P 121
  140. #define TEGRA20_CLK_PLL_P_OUT1 122
  141. #define TEGRA20_CLK_PLL_P_OUT2 123
  142. #define TEGRA20_CLK_PLL_P_OUT3 124
  143. #define TEGRA20_CLK_PLL_P_OUT4 125
  144. #define TEGRA20_CLK_PLL_S 126
  145. #define TEGRA20_CLK_PLL_U 127
  146. #define TEGRA20_CLK_PLL_X 128
  147. #define TEGRA20_CLK_COP 129 /* a/k/a avp */
  148. #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
  149. #define TEGRA20_CLK_PLL_REF 131
  150. #define TEGRA20_CLK_TWD 132
  151. #define TEGRA20_CLK_CLK_MAX 133
  152. #endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */