tegra186-clock.h 40 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /** @file */
  3. #ifndef _MACH_T186_CLK_T186_H
  4. #define _MACH_T186_CLK_T186_H
  5. /**
  6. * @defgroup clock_ids Clock Identifiers
  7. * @{
  8. * @defgroup extern_input external input clocks
  9. * @{
  10. * @def TEGRA186_CLK_OSC
  11. * @def TEGRA186_CLK_CLK_32K
  12. * @def TEGRA186_CLK_DTV_INPUT
  13. * @def TEGRA186_CLK_SOR0_PAD_CLKOUT
  14. * @def TEGRA186_CLK_SOR1_PAD_CLKOUT
  15. * @def TEGRA186_CLK_I2S1_SYNC_INPUT
  16. * @def TEGRA186_CLK_I2S2_SYNC_INPUT
  17. * @def TEGRA186_CLK_I2S3_SYNC_INPUT
  18. * @def TEGRA186_CLK_I2S4_SYNC_INPUT
  19. * @def TEGRA186_CLK_I2S5_SYNC_INPUT
  20. * @def TEGRA186_CLK_I2S6_SYNC_INPUT
  21. * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
  22. * @}
  23. *
  24. * @defgroup extern_output external output clocks
  25. * @{
  26. * @def TEGRA186_CLK_EXTPERIPH1
  27. * @def TEGRA186_CLK_EXTPERIPH2
  28. * @def TEGRA186_CLK_EXTPERIPH3
  29. * @def TEGRA186_CLK_EXTPERIPH4
  30. * @}
  31. *
  32. * @defgroup display_clks display related clocks
  33. * @{
  34. * @def TEGRA186_CLK_CEC
  35. * @def TEGRA186_CLK_DSIC
  36. * @def TEGRA186_CLK_DSIC_LP
  37. * @def TEGRA186_CLK_DSID
  38. * @def TEGRA186_CLK_DSID_LP
  39. * @def TEGRA186_CLK_DPAUX1
  40. * @def TEGRA186_CLK_DPAUX
  41. * @def TEGRA186_CLK_HDA2HDMICODEC
  42. * @def TEGRA186_CLK_NVDISPLAY_DISP
  43. * @def TEGRA186_CLK_NVDISPLAY_DSC
  44. * @def TEGRA186_CLK_NVDISPLAY_P0
  45. * @def TEGRA186_CLK_NVDISPLAY_P1
  46. * @def TEGRA186_CLK_NVDISPLAY_P2
  47. * @def TEGRA186_CLK_NVDISPLAYHUB
  48. * @def TEGRA186_CLK_SOR_SAFE
  49. * @def TEGRA186_CLK_SOR0
  50. * @def TEGRA186_CLK_SOR0_OUT
  51. * @def TEGRA186_CLK_SOR1
  52. * @def TEGRA186_CLK_SOR1_OUT
  53. * @def TEGRA186_CLK_DSI
  54. * @def TEGRA186_CLK_MIPI_CAL
  55. * @def TEGRA186_CLK_DSIA_LP
  56. * @def TEGRA186_CLK_DSIB
  57. * @def TEGRA186_CLK_DSIB_LP
  58. * @}
  59. *
  60. * @defgroup camera_clks camera related clocks
  61. * @{
  62. * @def TEGRA186_CLK_NVCSI
  63. * @def TEGRA186_CLK_NVCSILP
  64. * @def TEGRA186_CLK_VI
  65. * @}
  66. *
  67. * @defgroup audio_clks audio related clocks
  68. * @{
  69. * @def TEGRA186_CLK_ACLK
  70. * @def TEGRA186_CLK_ADSP
  71. * @def TEGRA186_CLK_ADSPNEON
  72. * @def TEGRA186_CLK_AHUB
  73. * @def TEGRA186_CLK_APE
  74. * @def TEGRA186_CLK_APB2APE
  75. * @def TEGRA186_CLK_AUD_MCLK
  76. * @def TEGRA186_CLK_DMIC1
  77. * @def TEGRA186_CLK_DMIC2
  78. * @def TEGRA186_CLK_DMIC3
  79. * @def TEGRA186_CLK_DMIC4
  80. * @def TEGRA186_CLK_DSPK1
  81. * @def TEGRA186_CLK_DSPK2
  82. * @def TEGRA186_CLK_HDA
  83. * @def TEGRA186_CLK_HDA2CODEC_2X
  84. * @def TEGRA186_CLK_I2S1
  85. * @def TEGRA186_CLK_I2S2
  86. * @def TEGRA186_CLK_I2S3
  87. * @def TEGRA186_CLK_I2S4
  88. * @def TEGRA186_CLK_I2S5
  89. * @def TEGRA186_CLK_I2S6
  90. * @def TEGRA186_CLK_MAUD
  91. * @def TEGRA186_CLK_PLL_A_OUT0
  92. * @def TEGRA186_CLK_SPDIF_DOUBLER
  93. * @def TEGRA186_CLK_SPDIF_IN
  94. * @def TEGRA186_CLK_SPDIF_OUT
  95. * @def TEGRA186_CLK_SYNC_DMIC1
  96. * @def TEGRA186_CLK_SYNC_DMIC2
  97. * @def TEGRA186_CLK_SYNC_DMIC3
  98. * @def TEGRA186_CLK_SYNC_DMIC4
  99. * @def TEGRA186_CLK_SYNC_DMIC5
  100. * @def TEGRA186_CLK_SYNC_DSPK1
  101. * @def TEGRA186_CLK_SYNC_DSPK2
  102. * @def TEGRA186_CLK_SYNC_I2S1
  103. * @def TEGRA186_CLK_SYNC_I2S2
  104. * @def TEGRA186_CLK_SYNC_I2S3
  105. * @def TEGRA186_CLK_SYNC_I2S4
  106. * @def TEGRA186_CLK_SYNC_I2S5
  107. * @def TEGRA186_CLK_SYNC_I2S6
  108. * @def TEGRA186_CLK_SYNC_SPDIF
  109. * @}
  110. *
  111. * @defgroup uart_clks UART clocks
  112. * @{
  113. * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
  114. * @def TEGRA186_CLK_UARTA
  115. * @def TEGRA186_CLK_UARTB
  116. * @def TEGRA186_CLK_UARTC
  117. * @def TEGRA186_CLK_UARTD
  118. * @def TEGRA186_CLK_UARTE
  119. * @def TEGRA186_CLK_UARTF
  120. * @def TEGRA186_CLK_UARTG
  121. * @def TEGRA186_CLK_UART_FST_MIPI_CAL
  122. * @}
  123. *
  124. * @defgroup i2c_clks I2C clocks
  125. * @{
  126. * @def TEGRA186_CLK_AON_I2C_SLOW
  127. * @def TEGRA186_CLK_I2C1
  128. * @def TEGRA186_CLK_I2C2
  129. * @def TEGRA186_CLK_I2C3
  130. * @def TEGRA186_CLK_I2C4
  131. * @def TEGRA186_CLK_I2C5
  132. * @def TEGRA186_CLK_I2C6
  133. * @def TEGRA186_CLK_I2C8
  134. * @def TEGRA186_CLK_I2C9
  135. * @def TEGRA186_CLK_I2C1
  136. * @def TEGRA186_CLK_I2C12
  137. * @def TEGRA186_CLK_I2C13
  138. * @def TEGRA186_CLK_I2C14
  139. * @def TEGRA186_CLK_I2C_SLOW
  140. * @def TEGRA186_CLK_VI_I2C
  141. * @}
  142. *
  143. * @defgroup spi_clks SPI clocks
  144. * @{
  145. * @def TEGRA186_CLK_SPI1
  146. * @def TEGRA186_CLK_SPI2
  147. * @def TEGRA186_CLK_SPI3
  148. * @def TEGRA186_CLK_SPI4
  149. * @}
  150. *
  151. * @defgroup storage storage related clocks
  152. * @{
  153. * @def TEGRA186_CLK_SATA
  154. * @def TEGRA186_CLK_SATA_OOB
  155. * @def TEGRA186_CLK_SATA_IOBIST
  156. * @def TEGRA186_CLK_SDMMC_LEGACY_TM
  157. * @def TEGRA186_CLK_SDMMC1
  158. * @def TEGRA186_CLK_SDMMC2
  159. * @def TEGRA186_CLK_SDMMC3
  160. * @def TEGRA186_CLK_SDMMC4
  161. * @def TEGRA186_CLK_QSPI
  162. * @def TEGRA186_CLK_QSPI_OUT
  163. * @def TEGRA186_CLK_UFSDEV_REF
  164. * @def TEGRA186_CLK_UFSHC
  165. * @}
  166. *
  167. * @defgroup pwm_clks PWM clocks
  168. * @{
  169. * @def TEGRA186_CLK_PWM1
  170. * @def TEGRA186_CLK_PWM2
  171. * @def TEGRA186_CLK_PWM3
  172. * @def TEGRA186_CLK_PWM4
  173. * @def TEGRA186_CLK_PWM5
  174. * @def TEGRA186_CLK_PWM6
  175. * @def TEGRA186_CLK_PWM7
  176. * @def TEGRA186_CLK_PWM8
  177. * @}
  178. *
  179. * @defgroup plls PLLs and related clocks
  180. * @{
  181. * @def TEGRA186_CLK_PLLREFE_OUT_GATED
  182. * @def TEGRA186_CLK_PLLREFE_OUT1
  183. * @def TEGRA186_CLK_PLLD_OUT1
  184. * @def TEGRA186_CLK_PLLP_OUT0
  185. * @def TEGRA186_CLK_PLLP_OUT5
  186. * @def TEGRA186_CLK_PLLA
  187. * @def TEGRA186_CLK_PLLE_PWRSEQ
  188. * @def TEGRA186_CLK_PLLA_OUT1
  189. * @def TEGRA186_CLK_PLLREFE_REF
  190. * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
  191. * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
  192. * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
  193. * @def TEGRA186_CLK_PLLREFE_PEX
  194. * @def TEGRA186_CLK_PLLREFE_IDDQ
  195. * @def TEGRA186_CLK_PLLC_OUT_AON
  196. * @def TEGRA186_CLK_PLLC_OUT_ISP
  197. * @def TEGRA186_CLK_PLLC_OUT_VE
  198. * @def TEGRA186_CLK_PLLC4_OUT
  199. * @def TEGRA186_CLK_PLLREFE_OUT
  200. * @def TEGRA186_CLK_PLLREFE_PLL_REF
  201. * @def TEGRA186_CLK_PLLE
  202. * @def TEGRA186_CLK_PLLC
  203. * @def TEGRA186_CLK_PLLP
  204. * @def TEGRA186_CLK_PLLD
  205. * @def TEGRA186_CLK_PLLD2
  206. * @def TEGRA186_CLK_PLLREFE_VCO
  207. * @def TEGRA186_CLK_PLLC2
  208. * @def TEGRA186_CLK_PLLC3
  209. * @def TEGRA186_CLK_PLLDP
  210. * @def TEGRA186_CLK_PLLC4_VCO
  211. * @def TEGRA186_CLK_PLLA1
  212. * @def TEGRA186_CLK_PLLNVCSI
  213. * @def TEGRA186_CLK_PLLDISPHUB
  214. * @def TEGRA186_CLK_PLLD3
  215. * @def TEGRA186_CLK_PLLBPMPCAM
  216. * @def TEGRA186_CLK_PLLAON
  217. * @def TEGRA186_CLK_PLLU
  218. * @def TEGRA186_CLK_PLLC4_VCO_DIV2
  219. * @def TEGRA186_CLK_PLL_REF
  220. * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
  221. * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
  222. * @def TEGRA186_CLK_PLL_U_48M
  223. * @def TEGRA186_CLK_PLL_U_480M
  224. * @def TEGRA186_CLK_PLLC4_OUT0
  225. * @def TEGRA186_CLK_PLLC4_OUT1
  226. * @def TEGRA186_CLK_PLLC4_OUT2
  227. * @def TEGRA186_CLK_PLLC4_OUT_MUX
  228. * @def TEGRA186_CLK_DFLLDISP_DIV
  229. * @def TEGRA186_CLK_PLLDISPHUB_DIV
  230. * @def TEGRA186_CLK_PLLP_DIV8
  231. * @}
  232. *
  233. * @defgroup nafll_clks NAFLL clock sources
  234. * @{
  235. * @def TEGRA186_CLK_NAFLL_AXI_CBB
  236. * @def TEGRA186_CLK_NAFLL_BCPU
  237. * @def TEGRA186_CLK_NAFLL_BPMP
  238. * @def TEGRA186_CLK_NAFLL_DISP
  239. * @def TEGRA186_CLK_NAFLL_GPU
  240. * @def TEGRA186_CLK_NAFLL_ISP
  241. * @def TEGRA186_CLK_NAFLL_MCPU
  242. * @def TEGRA186_CLK_NAFLL_NVDEC
  243. * @def TEGRA186_CLK_NAFLL_NVENC
  244. * @def TEGRA186_CLK_NAFLL_NVJPG
  245. * @def TEGRA186_CLK_NAFLL_SCE
  246. * @def TEGRA186_CLK_NAFLL_SE
  247. * @def TEGRA186_CLK_NAFLL_TSEC
  248. * @def TEGRA186_CLK_NAFLL_TSECB
  249. * @def TEGRA186_CLK_NAFLL_VI
  250. * @def TEGRA186_CLK_NAFLL_VIC
  251. * @}
  252. *
  253. * @defgroup mphy MPHY related clocks
  254. * @{
  255. * @def TEGRA186_CLK_MPHY_L0_RX_SYMB
  256. * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
  257. * @def TEGRA186_CLK_MPHY_L0_TX_SYMB
  258. * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
  259. * @def TEGRA186_CLK_MPHY_L0_RX_ANA
  260. * @def TEGRA186_CLK_MPHY_L1_RX_ANA
  261. * @def TEGRA186_CLK_MPHY_IOBIST
  262. * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
  263. * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
  264. * @}
  265. *
  266. * @defgroup eavb EAVB related clocks
  267. * @{
  268. * @def TEGRA186_CLK_EQOS_AXI
  269. * @def TEGRA186_CLK_EQOS_PTP_REF
  270. * @def TEGRA186_CLK_EQOS_RX
  271. * @def TEGRA186_CLK_EQOS_RX_INPUT
  272. * @def TEGRA186_CLK_EQOS_TX
  273. * @}
  274. *
  275. * @defgroup usb USB related clocks
  276. * @{
  277. * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
  278. * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
  279. * @def TEGRA186_CLK_HSIC_TRK
  280. * @def TEGRA186_CLK_USB2_TRK
  281. * @def TEGRA186_CLK_USB2_HSIC_TRK
  282. * @def TEGRA186_CLK_XUSB_CORE_SS
  283. * @def TEGRA186_CLK_XUSB_CORE_DEV
  284. * @def TEGRA186_CLK_XUSB_FALCON
  285. * @def TEGRA186_CLK_XUSB_FS
  286. * @def TEGRA186_CLK_XUSB
  287. * @def TEGRA186_CLK_XUSB_DEV
  288. * @def TEGRA186_CLK_XUSB_HOST
  289. * @def TEGRA186_CLK_XUSB_SS
  290. * @}
  291. *
  292. * @defgroup bigblock compute block related clocks
  293. * @{
  294. * @def TEGRA186_CLK_GPCCLK
  295. * @def TEGRA186_CLK_GPC2CLK
  296. * @def TEGRA186_CLK_GPU
  297. * @def TEGRA186_CLK_HOST1X
  298. * @def TEGRA186_CLK_ISP
  299. * @def TEGRA186_CLK_NVDEC
  300. * @def TEGRA186_CLK_NVENC
  301. * @def TEGRA186_CLK_NVJPG
  302. * @def TEGRA186_CLK_SE
  303. * @def TEGRA186_CLK_TSEC
  304. * @def TEGRA186_CLK_TSECB
  305. * @def TEGRA186_CLK_VIC
  306. * @}
  307. *
  308. * @defgroup can CAN bus related clocks
  309. * @{
  310. * @def TEGRA186_CLK_CAN1
  311. * @def TEGRA186_CLK_CAN1_HOST
  312. * @def TEGRA186_CLK_CAN2
  313. * @def TEGRA186_CLK_CAN2_HOST
  314. * @}
  315. *
  316. * @defgroup system basic system clocks
  317. * @{
  318. * @def TEGRA186_CLK_ACTMON
  319. * @def TEGRA186_CLK_AON_APB
  320. * @def TEGRA186_CLK_AON_CPU_NIC
  321. * @def TEGRA186_CLK_AON_NIC
  322. * @def TEGRA186_CLK_AXI_CBB
  323. * @def TEGRA186_CLK_BPMP_APB
  324. * @def TEGRA186_CLK_BPMP_CPU_NIC
  325. * @def TEGRA186_CLK_BPMP_NIC_RATE
  326. * @def TEGRA186_CLK_CLK_M
  327. * @def TEGRA186_CLK_EMC
  328. * @def TEGRA186_CLK_MSS_ENCRYPT
  329. * @def TEGRA186_CLK_SCE_APB
  330. * @def TEGRA186_CLK_SCE_CPU_NIC
  331. * @def TEGRA186_CLK_SCE_NIC
  332. * @def TEGRA186_CLK_TSC
  333. * @}
  334. *
  335. * @defgroup pcie_clks PCIe related clocks
  336. * @{
  337. * @def TEGRA186_CLK_AFI
  338. * @def TEGRA186_CLK_PCIE
  339. * @def TEGRA186_CLK_PCIE2_IOBIST
  340. * @def TEGRA186_CLK_PCIERX0
  341. * @def TEGRA186_CLK_PCIERX1
  342. * @def TEGRA186_CLK_PCIERX2
  343. * @def TEGRA186_CLK_PCIERX3
  344. * @def TEGRA186_CLK_PCIERX4
  345. * @}
  346. */
  347. /** @brief output of gate CLK_ENB_FUSE */
  348. #define TEGRA186_CLK_FUSE 0
  349. /**
  350. * @brief It's not what you think
  351. * @details output of gate CLK_ENB_GPU. This output connects to the GPU
  352. * pwrclk. @warning: This is almost certainly not the clock you think
  353. * it is. If you're looking for the clock of the graphics engine, see
  354. * TEGRA186_GPCCLK
  355. */
  356. #define TEGRA186_CLK_GPU 1
  357. /** @brief output of gate CLK_ENB_PCIE */
  358. #define TEGRA186_CLK_PCIE 3
  359. /** @brief output of the divider IPFS_CLK_DIVISOR */
  360. #define TEGRA186_CLK_AFI 4
  361. /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
  362. #define TEGRA186_CLK_PCIE2_IOBIST 5
  363. /** @brief output of gate CLK_ENB_PCIERX0*/
  364. #define TEGRA186_CLK_PCIERX0 6
  365. /** @brief output of gate CLK_ENB_PCIERX1*/
  366. #define TEGRA186_CLK_PCIERX1 7
  367. /** @brief output of gate CLK_ENB_PCIERX2*/
  368. #define TEGRA186_CLK_PCIERX2 8
  369. /** @brief output of gate CLK_ENB_PCIERX3*/
  370. #define TEGRA186_CLK_PCIERX3 9
  371. /** @brief output of gate CLK_ENB_PCIERX4*/
  372. #define TEGRA186_CLK_PCIERX4 10
  373. /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
  374. #define TEGRA186_CLK_PLLC_OUT_ISP 11
  375. /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
  376. #define TEGRA186_CLK_PLLC_OUT_VE 12
  377. /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
  378. #define TEGRA186_CLK_PLLC_OUT_AON 13
  379. /** @brief output of gate CLK_ENB_SOR_SAFE */
  380. #define TEGRA186_CLK_SOR_SAFE 39
  381. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
  382. #define TEGRA186_CLK_I2S2 42
  383. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
  384. #define TEGRA186_CLK_I2S3 43
  385. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
  386. #define TEGRA186_CLK_SPDIF_IN 44
  387. /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
  388. #define TEGRA186_CLK_SPDIF_DOUBLER 45
  389. /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
  390. #define TEGRA186_CLK_SPI3 46
  391. /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
  392. #define TEGRA186_CLK_I2C1 47
  393. /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
  394. #define TEGRA186_CLK_I2C5 48
  395. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
  396. #define TEGRA186_CLK_SPI1 49
  397. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
  398. #define TEGRA186_CLK_ISP 50
  399. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
  400. #define TEGRA186_CLK_VI 51
  401. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
  402. #define TEGRA186_CLK_SDMMC1 52
  403. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
  404. #define TEGRA186_CLK_SDMMC2 53
  405. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
  406. #define TEGRA186_CLK_SDMMC4 54
  407. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
  408. #define TEGRA186_CLK_UARTA 55
  409. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
  410. #define TEGRA186_CLK_UARTB 56
  411. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
  412. #define TEGRA186_CLK_HOST1X 57
  413. /**
  414. * @brief controls the EMC clock frequency.
  415. * @details Doing a clk_set_rate on this clock will select the
  416. * appropriate clock source, program the source rate and execute a
  417. * specific sequence to switch to the new clock source for both memory
  418. * controllers. This can be used to control the balance between memory
  419. * throughput and memory controller power.
  420. */
  421. #define TEGRA186_CLK_EMC 58
  422. /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
  423. #define TEGRA186_CLK_EXTPERIPH4 73
  424. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
  425. #define TEGRA186_CLK_SPI4 74
  426. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
  427. #define TEGRA186_CLK_I2C3 75
  428. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
  429. #define TEGRA186_CLK_SDMMC3 76
  430. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
  431. #define TEGRA186_CLK_UARTD 77
  432. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
  433. #define TEGRA186_CLK_I2S1 79
  434. /** output of gate CLK_ENB_DTV */
  435. #define TEGRA186_CLK_DTV 80
  436. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
  437. #define TEGRA186_CLK_TSEC 81
  438. /** @brief output of gate CLK_ENB_DP2 */
  439. #define TEGRA186_CLK_DP2 82
  440. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
  441. #define TEGRA186_CLK_I2S4 84
  442. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
  443. #define TEGRA186_CLK_I2S5 85
  444. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
  445. #define TEGRA186_CLK_I2C4 86
  446. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
  447. #define TEGRA186_CLK_AHUB 87
  448. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
  449. #define TEGRA186_CLK_HDA2CODEC_2X 88
  450. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
  451. #define TEGRA186_CLK_EXTPERIPH1 89
  452. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
  453. #define TEGRA186_CLK_EXTPERIPH2 90
  454. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
  455. #define TEGRA186_CLK_EXTPERIPH3 91
  456. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
  457. #define TEGRA186_CLK_I2C_SLOW 92
  458. /** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
  459. #define TEGRA186_CLK_SOR1 93
  460. /** @brief output of gate CLK_ENB_CEC */
  461. #define TEGRA186_CLK_CEC 94
  462. /** @brief output of gate CLK_ENB_DPAUX1 */
  463. #define TEGRA186_CLK_DPAUX1 95
  464. /** @brief output of gate CLK_ENB_DPAUX */
  465. #define TEGRA186_CLK_DPAUX 96
  466. /** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
  467. #define TEGRA186_CLK_SOR0 97
  468. /** @brief output of gate CLK_ENB_HDA2HDMICODEC */
  469. #define TEGRA186_CLK_HDA2HDMICODEC 98
  470. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
  471. #define TEGRA186_CLK_SATA 99
  472. /** @brief output of gate CLK_ENB_SATA_OOB */
  473. #define TEGRA186_CLK_SATA_OOB 100
  474. /** @brief output of gate CLK_ENB_SATA_IOBIST */
  475. #define TEGRA186_CLK_SATA_IOBIST 101
  476. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
  477. #define TEGRA186_CLK_HDA 102
  478. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
  479. #define TEGRA186_CLK_SE 103
  480. /** @brief output of gate CLK_ENB_APB2APE */
  481. #define TEGRA186_CLK_APB2APE 104
  482. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
  483. #define TEGRA186_CLK_APE 105
  484. /** @brief output of gate CLK_ENB_IQC1 */
  485. #define TEGRA186_CLK_IQC1 106
  486. /** @brief output of gate CLK_ENB_IQC2 */
  487. #define TEGRA186_CLK_IQC2 107
  488. /** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
  489. #define TEGRA186_CLK_PLLREFE_OUT 108
  490. /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
  491. #define TEGRA186_CLK_PLLREFE_PLL_REF 109
  492. /** @brief output of gate CLK_ENB_PLLC4_OUT */
  493. #define TEGRA186_CLK_PLLC4_OUT 110
  494. /** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
  495. #define TEGRA186_CLK_XUSB 111
  496. /** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
  497. #define TEGRA186_CLK_XUSB_DEV 112
  498. /** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
  499. #define TEGRA186_CLK_XUSB_HOST 113
  500. /** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
  501. #define TEGRA186_CLK_XUSB_SS 114
  502. /** @brief output of gate CLK_ENB_DSI */
  503. #define TEGRA186_CLK_DSI 115
  504. /** @brief output of gate CLK_ENB_MIPI_CAL */
  505. #define TEGRA186_CLK_MIPI_CAL 116
  506. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
  507. #define TEGRA186_CLK_DSIA_LP 117
  508. /** @brief output of gate CLK_ENB_DSIB */
  509. #define TEGRA186_CLK_DSIB 118
  510. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
  511. #define TEGRA186_CLK_DSIB_LP 119
  512. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
  513. #define TEGRA186_CLK_DMIC1 122
  514. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
  515. #define TEGRA186_CLK_DMIC2 123
  516. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
  517. #define TEGRA186_CLK_AUD_MCLK 124
  518. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
  519. #define TEGRA186_CLK_I2C6 125
  520. /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
  521. #define TEGRA186_CLK_UART_FST_MIPI_CAL 126
  522. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
  523. #define TEGRA186_CLK_VIC 127
  524. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
  525. #define TEGRA186_CLK_SDMMC_LEGACY_TM 128
  526. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
  527. #define TEGRA186_CLK_NVDEC 129
  528. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
  529. #define TEGRA186_CLK_NVJPG 130
  530. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
  531. #define TEGRA186_CLK_NVENC 131
  532. /** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
  533. #define TEGRA186_CLK_QSPI 132
  534. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
  535. #define TEGRA186_CLK_VI_I2C 133
  536. /** @brief output of gate CLK_ENB_HSIC_TRK */
  537. #define TEGRA186_CLK_HSIC_TRK 134
  538. /** @brief output of gate CLK_ENB_USB2_TRK */
  539. #define TEGRA186_CLK_USB2_TRK 135
  540. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
  541. #define TEGRA186_CLK_MAUD 136
  542. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
  543. #define TEGRA186_CLK_TSECB 137
  544. /** @brief output of gate CLK_ENB_ADSP */
  545. #define TEGRA186_CLK_ADSP 138
  546. /** @brief output of gate CLK_ENB_ADSPNEON */
  547. #define TEGRA186_CLK_ADSPNEON 139
  548. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
  549. #define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
  550. /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
  551. #define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
  552. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
  553. #define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
  554. /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
  555. #define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
  556. /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
  557. #define TEGRA186_CLK_MPHY_L0_RX_ANA 144
  558. /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
  559. #define TEGRA186_CLK_MPHY_L1_RX_ANA 145
  560. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
  561. #define TEGRA186_CLK_MPHY_IOBIST 146
  562. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
  563. #define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
  564. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
  565. #define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
  566. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
  567. #define TEGRA186_CLK_AXI_CBB 149
  568. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
  569. #define TEGRA186_CLK_DMIC3 150
  570. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
  571. #define TEGRA186_CLK_DMIC4 151
  572. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
  573. #define TEGRA186_CLK_DSPK1 152
  574. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
  575. #define TEGRA186_CLK_DSPK2 153
  576. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
  577. #define TEGRA186_CLK_I2S6 154
  578. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
  579. #define TEGRA186_CLK_NVDISPLAY_P0 155
  580. /** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
  581. #define TEGRA186_CLK_NVDISPLAY_DISP 156
  582. /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
  583. #define TEGRA186_CLK_NVDISPLAY_DSC 157
  584. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
  585. #define TEGRA186_CLK_NVDISPLAYHUB 158
  586. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
  587. #define TEGRA186_CLK_NVDISPLAY_P1 159
  588. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
  589. #define TEGRA186_CLK_NVDISPLAY_P2 160
  590. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
  591. #define TEGRA186_CLK_TACH 166
  592. /** @brief output of gate CLK_ENB_EQOS */
  593. #define TEGRA186_CLK_EQOS_AXI 167
  594. /** @brief output of gate CLK_ENB_EQOS_RX */
  595. #define TEGRA186_CLK_EQOS_RX 168
  596. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
  597. #define TEGRA186_CLK_UFSHC 178
  598. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
  599. #define TEGRA186_CLK_UFSDEV_REF 179
  600. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
  601. #define TEGRA186_CLK_NVCSI 180
  602. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
  603. #define TEGRA186_CLK_NVCSILP 181
  604. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
  605. #define TEGRA186_CLK_I2C7 182
  606. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
  607. #define TEGRA186_CLK_I2C9 183
  608. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
  609. #define TEGRA186_CLK_I2C12 184
  610. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
  611. #define TEGRA186_CLK_I2C13 185
  612. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
  613. #define TEGRA186_CLK_I2C14 186
  614. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
  615. #define TEGRA186_CLK_PWM1 187
  616. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
  617. #define TEGRA186_CLK_PWM2 188
  618. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
  619. #define TEGRA186_CLK_PWM3 189
  620. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
  621. #define TEGRA186_CLK_PWM5 190
  622. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
  623. #define TEGRA186_CLK_PWM6 191
  624. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
  625. #define TEGRA186_CLK_PWM7 192
  626. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
  627. #define TEGRA186_CLK_PWM8 193
  628. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
  629. #define TEGRA186_CLK_UARTE 194
  630. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
  631. #define TEGRA186_CLK_UARTF 195
  632. /** @deprecated */
  633. #define TEGRA186_CLK_DBGAPB 196
  634. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
  635. #define TEGRA186_CLK_BPMP_CPU_NIC 197
  636. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
  637. #define TEGRA186_CLK_BPMP_APB 199
  638. /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
  639. #define TEGRA186_CLK_ACTMON 201
  640. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
  641. #define TEGRA186_CLK_AON_CPU_NIC 208
  642. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
  643. #define TEGRA186_CLK_CAN1 210
  644. /** @brief output of gate CLK_ENB_CAN1_HOST */
  645. #define TEGRA186_CLK_CAN1_HOST 211
  646. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
  647. #define TEGRA186_CLK_CAN2 212
  648. /** @brief output of gate CLK_ENB_CAN2_HOST */
  649. #define TEGRA186_CLK_CAN2_HOST 213
  650. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
  651. #define TEGRA186_CLK_AON_APB 214
  652. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
  653. #define TEGRA186_CLK_UARTC 215
  654. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
  655. #define TEGRA186_CLK_UARTG 216
  656. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
  657. #define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
  658. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
  659. #define TEGRA186_CLK_I2C2 218
  660. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
  661. #define TEGRA186_CLK_I2C8 219
  662. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
  663. #define TEGRA186_CLK_I2C10 220
  664. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
  665. #define TEGRA186_CLK_AON_I2C_SLOW 221
  666. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
  667. #define TEGRA186_CLK_SPI2 222
  668. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
  669. #define TEGRA186_CLK_DMIC5 223
  670. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
  671. #define TEGRA186_CLK_AON_TOUCH 224
  672. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
  673. #define TEGRA186_CLK_PWM4 225
  674. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
  675. #define TEGRA186_CLK_TSC 226
  676. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
  677. #define TEGRA186_CLK_MSS_ENCRYPT 227
  678. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
  679. #define TEGRA186_CLK_SCE_CPU_NIC 228
  680. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
  681. #define TEGRA186_CLK_SCE_APB 230
  682. /** @brief output of gate CLK_ENB_DSIC */
  683. #define TEGRA186_CLK_DSIC 231
  684. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
  685. #define TEGRA186_CLK_DSIC_LP 232
  686. /** @brief output of gate CLK_ENB_DSID */
  687. #define TEGRA186_CLK_DSID 233
  688. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
  689. #define TEGRA186_CLK_DSID_LP 234
  690. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
  691. #define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
  692. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
  693. #define TEGRA186_CLK_SPDIF_OUT 238
  694. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
  695. #define TEGRA186_CLK_EQOS_PTP_REF 239
  696. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
  697. #define TEGRA186_CLK_EQOS_TX 240
  698. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
  699. #define TEGRA186_CLK_USB2_HSIC_TRK 241
  700. /** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
  701. #define TEGRA186_CLK_XUSB_CORE_SS 242
  702. /** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
  703. #define TEGRA186_CLK_XUSB_CORE_DEV 243
  704. /** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
  705. #define TEGRA186_CLK_XUSB_FALCON 244
  706. /** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
  707. #define TEGRA186_CLK_XUSB_FS 245
  708. /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
  709. #define TEGRA186_CLK_PLL_A_OUT0 246
  710. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
  711. #define TEGRA186_CLK_SYNC_I2S1 247
  712. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
  713. #define TEGRA186_CLK_SYNC_I2S2 248
  714. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
  715. #define TEGRA186_CLK_SYNC_I2S3 249
  716. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
  717. #define TEGRA186_CLK_SYNC_I2S4 250
  718. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
  719. #define TEGRA186_CLK_SYNC_I2S5 251
  720. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
  721. #define TEGRA186_CLK_SYNC_I2S6 252
  722. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
  723. #define TEGRA186_CLK_SYNC_DSPK1 253
  724. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
  725. #define TEGRA186_CLK_SYNC_DSPK2 254
  726. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
  727. #define TEGRA186_CLK_SYNC_DMIC1 255
  728. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
  729. #define TEGRA186_CLK_SYNC_DMIC2 256
  730. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
  731. #define TEGRA186_CLK_SYNC_DMIC3 257
  732. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
  733. #define TEGRA186_CLK_SYNC_DMIC4 259
  734. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
  735. #define TEGRA186_CLK_SYNC_SPDIF 260
  736. /** @brief output of gate CLK_ENB_PLLREFE_OUT */
  737. #define TEGRA186_CLK_PLLREFE_OUT_GATED 261
  738. /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
  739. * * VCO/pdiv defined by this clock object
  740. * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
  741. */
  742. #define TEGRA186_CLK_PLLREFE_OUT1 262
  743. #define TEGRA186_CLK_PLLD_OUT1 267
  744. /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
  745. #define TEGRA186_CLK_PLLP_OUT0 269
  746. /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
  747. #define TEGRA186_CLK_PLLP_OUT5 270
  748. /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
  749. #define TEGRA186_CLK_PLLA 271
  750. /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
  751. #define TEGRA186_CLK_ACLK 273
  752. /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
  753. #define TEGRA186_CLK_PLL_U_48M 274
  754. /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
  755. #define TEGRA186_CLK_PLL_U_480M 275
  756. /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
  757. #define TEGRA186_CLK_PLLC4_OUT0 276
  758. /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
  759. #define TEGRA186_CLK_PLLC4_OUT1 277
  760. /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
  761. #define TEGRA186_CLK_PLLC4_OUT2 278
  762. /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
  763. #define TEGRA186_CLK_PLLC4_OUT_MUX 279
  764. /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
  765. #define TEGRA186_CLK_DFLLDISP_DIV 284
  766. /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
  767. #define TEGRA186_CLK_PLLDISPHUB_DIV 285
  768. /** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
  769. #define TEGRA186_CLK_PLLP_DIV8 286
  770. /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
  771. #define TEGRA186_CLK_BPMP_NIC 287
  772. /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
  773. #define TEGRA186_CLK_PLL_A_OUT1 288
  774. /** @deprecated */
  775. #define TEGRA186_CLK_GPC2CLK 289
  776. /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
  777. #define TEGRA186_CLK_KFUSE 293
  778. /**
  779. * @brief controls the PLLE hardware sequencer.
  780. * @details This clock only has enable and disable methods. When the
  781. * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
  782. * hw based on the control signals from the PCIe, SATA and XUSB
  783. * clocks. When the PLLE hw sequencer is disabled, the state of PLLE
  784. * is controlled by sw using clk_enable/clk_disable on
  785. * TEGRA186_CLK_PLLE.
  786. */
  787. #define TEGRA186_CLK_PLLE_PWRSEQ 294
  788. /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
  789. #define TEGRA186_CLK_PLLREFE_REF 295
  790. /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
  791. #define TEGRA186_CLK_SOR0_OUT 296
  792. /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
  793. #define TEGRA186_CLK_SOR1_OUT 297
  794. /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
  795. #define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
  796. /** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
  797. #define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
  798. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
  799. #define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
  800. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
  801. #define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
  802. /** @brief controls the UPHY_PLL0 hardware sqeuencer */
  803. #define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
  804. /** @brief controls the UPHY_PLL1 hardware sqeuencer */
  805. #define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
  806. /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
  807. #define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
  808. /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
  809. #define TEGRA186_CLK_PLLREFE_PEX 307
  810. /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
  811. #define TEGRA186_CLK_PLLREFE_IDDQ 308
  812. /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
  813. #define TEGRA186_CLK_QSPI_OUT 309
  814. /**
  815. * @brief GPC2CLK-div-2
  816. * @details fixed /2 divider. Output frequency is
  817. * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
  818. * frequency at which the GPU graphics engine runs. */
  819. #define TEGRA186_CLK_GPCCLK 310
  820. /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
  821. #define TEGRA186_CLK_AON_NIC 450
  822. /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
  823. #define TEGRA186_CLK_SCE_NIC 451
  824. /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
  825. #define TEGRA186_CLK_PLLE 512
  826. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
  827. #define TEGRA186_CLK_PLLC 513
  828. /** Fixed 408MHz PLL for use by peripheral clocks */
  829. #define TEGRA186_CLK_PLLP 516
  830. /** @deprecated */
  831. #define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
  832. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
  833. #define TEGRA186_CLK_PLLD 518
  834. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
  835. #define TEGRA186_CLK_PLLD2 519
  836. /**
  837. * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
  838. * @details Note that this clock only controls the VCO output, before
  839. * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
  840. * information.
  841. */
  842. #define TEGRA186_CLK_PLLREFE_VCO 520
  843. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
  844. #define TEGRA186_CLK_PLLC2 521
  845. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
  846. #define TEGRA186_CLK_PLLC3 522
  847. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
  848. #define TEGRA186_CLK_PLLDP 523
  849. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
  850. #define TEGRA186_CLK_PLLC4_VCO 524
  851. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
  852. #define TEGRA186_CLK_PLLA1 525
  853. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
  854. #define TEGRA186_CLK_PLLNVCSI 526
  855. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
  856. #define TEGRA186_CLK_PLLDISPHUB 527
  857. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
  858. #define TEGRA186_CLK_PLLD3 528
  859. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
  860. #define TEGRA186_CLK_PLLBPMPCAM 531
  861. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
  862. #define TEGRA186_CLK_PLLAON 532
  863. /** Fixed frequency 960MHz PLL for USB and EAVB */
  864. #define TEGRA186_CLK_PLLU 533
  865. /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
  866. #define TEGRA186_CLK_PLLC4_VCO_DIV2 535
  867. /** @brief NAFLL clock source for AXI_CBB */
  868. #define TEGRA186_CLK_NAFLL_AXI_CBB 564
  869. /** @brief NAFLL clock source for BPMP */
  870. #define TEGRA186_CLK_NAFLL_BPMP 565
  871. /** @brief NAFLL clock source for ISP */
  872. #define TEGRA186_CLK_NAFLL_ISP 566
  873. /** @brief NAFLL clock source for NVDEC */
  874. #define TEGRA186_CLK_NAFLL_NVDEC 567
  875. /** @brief NAFLL clock source for NVENC */
  876. #define TEGRA186_CLK_NAFLL_NVENC 568
  877. /** @brief NAFLL clock source for NVJPG */
  878. #define TEGRA186_CLK_NAFLL_NVJPG 569
  879. /** @brief NAFLL clock source for SCE */
  880. #define TEGRA186_CLK_NAFLL_SCE 570
  881. /** @brief NAFLL clock source for SE */
  882. #define TEGRA186_CLK_NAFLL_SE 571
  883. /** @brief NAFLL clock source for TSEC */
  884. #define TEGRA186_CLK_NAFLL_TSEC 572
  885. /** @brief NAFLL clock source for TSECB */
  886. #define TEGRA186_CLK_NAFLL_TSECB 573
  887. /** @brief NAFLL clock source for VI */
  888. #define TEGRA186_CLK_NAFLL_VI 574
  889. /** @brief NAFLL clock source for VIC */
  890. #define TEGRA186_CLK_NAFLL_VIC 575
  891. /** @brief NAFLL clock source for DISP */
  892. #define TEGRA186_CLK_NAFLL_DISP 576
  893. /** @brief NAFLL clock source for GPU */
  894. #define TEGRA186_CLK_NAFLL_GPU 577
  895. /** @brief NAFLL clock source for M-CPU cluster */
  896. #define TEGRA186_CLK_NAFLL_MCPU 578
  897. /** @brief NAFLL clock source for B-CPU cluster */
  898. #define TEGRA186_CLK_NAFLL_BCPU 579
  899. /** @brief input from Tegra's CLK_32K_IN pad */
  900. #define TEGRA186_CLK_CLK_32K 608
  901. /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
  902. #define TEGRA186_CLK_CLK_M 609
  903. /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
  904. #define TEGRA186_CLK_PLL_REF 610
  905. /** @brief input from Tegra's XTAL_IN */
  906. #define TEGRA186_CLK_OSC 612
  907. /** @brief clock recovered from EAVB input */
  908. #define TEGRA186_CLK_EQOS_RX_INPUT 613
  909. /** @brief clock recovered from DTV input */
  910. #define TEGRA186_CLK_DTV_INPUT 614
  911. /** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
  912. #define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
  913. /** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
  914. #define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
  915. /** @brief clock recovered from I2S1 input */
  916. #define TEGRA186_CLK_I2S1_SYNC_INPUT 617
  917. /** @brief clock recovered from I2S2 input */
  918. #define TEGRA186_CLK_I2S2_SYNC_INPUT 618
  919. /** @brief clock recovered from I2S3 input */
  920. #define TEGRA186_CLK_I2S3_SYNC_INPUT 619
  921. /** @brief clock recovered from I2S4 input */
  922. #define TEGRA186_CLK_I2S4_SYNC_INPUT 620
  923. /** @brief clock recovered from I2S5 input */
  924. #define TEGRA186_CLK_I2S5_SYNC_INPUT 621
  925. /** @brief clock recovered from I2S6 input */
  926. #define TEGRA186_CLK_I2S6_SYNC_INPUT 622
  927. /** @brief clock recovered from SPDIFIN input */
  928. #define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
  929. /**
  930. * @brief subject to change
  931. * @details maximum clock identifier value plus one.
  932. */
  933. #define TEGRA186_CLK_CLK_MAX 624
  934. /** @} */
  935. #endif