s3c2412.h 1.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  4. *
  5. * Device Tree binding constants clock controllers of Samsung S3C2412.
  6. */
  7. #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
  8. #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
  9. /*
  10. * Let each exported clock get a unique index, which is used on DT-enabled
  11. * platforms to lookup the clock from a clock specifier. These indices are
  12. * therefore considered an ABI and so must not be changed. This implies
  13. * that new clocks should be added either in free spaces between clock groups
  14. * or at the end.
  15. */
  16. /* Core clocks. */
  17. /* id 1 is reserved */
  18. #define MPLL 2
  19. #define UPLL 3
  20. #define MDIVCLK 4
  21. #define MSYSCLK 5
  22. #define USYSCLK 6
  23. #define HCLK 7
  24. #define PCLK 8
  25. #define ARMDIV 9
  26. #define ARMCLK 10
  27. /* Special clocks */
  28. #define SCLK_CAM 16
  29. #define SCLK_UART 17
  30. #define SCLK_I2S 18
  31. #define SCLK_USBD 19
  32. #define SCLK_USBH 20
  33. /* pclk-gates */
  34. #define PCLK_WDT 32
  35. #define PCLK_SPI 33
  36. #define PCLK_I2S 34
  37. #define PCLK_I2C 35
  38. #define PCLK_ADC 36
  39. #define PCLK_RTC 37
  40. #define PCLK_GPIO 38
  41. #define PCLK_UART2 39
  42. #define PCLK_UART1 40
  43. #define PCLK_UART0 41
  44. #define PCLK_SDI 42
  45. #define PCLK_PWM 43
  46. #define PCLK_USBD 44
  47. /* hclk-gates */
  48. #define HCLK_HALF 48
  49. #define HCLK_X2 49
  50. #define HCLK_SDRAM 50
  51. #define HCLK_USBH 51
  52. #define HCLK_LCD 52
  53. #define HCLK_NAND 53
  54. #define HCLK_DMA3 54
  55. #define HCLK_DMA2 55
  56. #define HCLK_DMA1 56
  57. #define HCLK_DMA0 57
  58. /* Total number of clocks. */
  59. #define NR_CLKS (HCLK_DMA0 + 1)
  60. #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */