s3c2410.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  4. *
  5. * Device Tree binding constants clock controllers of Samsung S3C2410 and later.
  6. */
  7. #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
  8. #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
  9. /*
  10. * Let each exported clock get a unique index, which is used on DT-enabled
  11. * platforms to lookup the clock from a clock specifier. These indices are
  12. * therefore considered an ABI and so must not be changed. This implies
  13. * that new clocks should be added either in free spaces between clock groups
  14. * or at the end.
  15. */
  16. /* Core clocks. */
  17. /* id 1 is reserved */
  18. #define MPLL 2
  19. #define UPLL 3
  20. #define FCLK 4
  21. #define HCLK 5
  22. #define PCLK 6
  23. #define UCLK 7
  24. #define ARMCLK 8
  25. /* pclk-gates */
  26. #define PCLK_UART0 16
  27. #define PCLK_UART1 17
  28. #define PCLK_UART2 18
  29. #define PCLK_I2C 19
  30. #define PCLK_SDI 20
  31. #define PCLK_SPI 21
  32. #define PCLK_ADC 22
  33. #define PCLK_AC97 23
  34. #define PCLK_I2S 24
  35. #define PCLK_PWM 25
  36. #define PCLK_RTC 26
  37. #define PCLK_GPIO 27
  38. /* hclk-gates */
  39. #define HCLK_LCD 32
  40. #define HCLK_USBH 33
  41. #define HCLK_USBD 34
  42. #define HCLK_NAND 35
  43. #define HCLK_CAM 36
  44. #define CAMIF 40
  45. /* Total number of clocks. */
  46. #define NR_CLKS (CAMIF + 1)
  47. #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */