rk3128-cru.h 6.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
  4. * Author: Elaine <zhangqing@rock-chips.com>
  5. */
  6. #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
  7. #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
  8. /* core clocks */
  9. #define PLL_APLL 1
  10. #define PLL_DPLL 2
  11. #define PLL_CPLL 3
  12. #define PLL_GPLL 4
  13. #define ARMCLK 5
  14. #define PLL_GPLL_DIV2 6
  15. #define PLL_GPLL_DIV3 7
  16. /* sclk gates (special clocks) */
  17. #define SCLK_SPI0 65
  18. #define SCLK_NANDC 67
  19. #define SCLK_SDMMC 68
  20. #define SCLK_SDIO 69
  21. #define SCLK_EMMC 71
  22. #define SCLK_UART0 77
  23. #define SCLK_UART1 78
  24. #define SCLK_UART2 79
  25. #define SCLK_I2S0 80
  26. #define SCLK_I2S1 81
  27. #define SCLK_SPDIF 83
  28. #define SCLK_TIMER0 85
  29. #define SCLK_TIMER1 86
  30. #define SCLK_TIMER2 87
  31. #define SCLK_TIMER3 88
  32. #define SCLK_TIMER4 89
  33. #define SCLK_TIMER5 90
  34. #define SCLK_SARADC 91
  35. #define SCLK_I2S_OUT 113
  36. #define SCLK_SDMMC_DRV 114
  37. #define SCLK_SDIO_DRV 115
  38. #define SCLK_EMMC_DRV 117
  39. #define SCLK_SDMMC_SAMPLE 118
  40. #define SCLK_SDIO_SAMPLE 119
  41. #define SCLK_EMMC_SAMPLE 121
  42. #define SCLK_VOP 122
  43. #define SCLK_MAC_SRC 124
  44. #define SCLK_MAC 126
  45. #define SCLK_MAC_REFOUT 127
  46. #define SCLK_MAC_REF 128
  47. #define SCLK_MAC_RX 129
  48. #define SCLK_MAC_TX 130
  49. #define SCLK_HEVC_CORE 134
  50. #define SCLK_RGA 135
  51. #define SCLK_CRYPTO 138
  52. #define SCLK_TSP 139
  53. #define SCLK_OTGPHY0 142
  54. #define SCLK_OTGPHY1 143
  55. #define SCLK_DDRC 144
  56. #define SCLK_PVTM_FUNC 145
  57. #define SCLK_PVTM_CORE 146
  58. #define SCLK_PVTM_GPU 147
  59. #define SCLK_MIPI_24M 148
  60. #define SCLK_PVTM 149
  61. #define SCLK_CIF_SRC 150
  62. #define SCLK_CIF_OUT_SRC 151
  63. #define SCLK_CIF_OUT 152
  64. #define SCLK_SFC 153
  65. #define SCLK_USB480M 154
  66. /* dclk gates */
  67. #define DCLK_VOP 190
  68. #define DCLK_EBC 191
  69. /* aclk gates */
  70. #define ACLK_VIO0 192
  71. #define ACLK_VIO1 193
  72. #define ACLK_DMAC 194
  73. #define ACLK_CPU 195
  74. #define ACLK_VEPU 196
  75. #define ACLK_VDPU 197
  76. #define ACLK_CIF 198
  77. #define ACLK_IEP 199
  78. #define ACLK_LCDC0 204
  79. #define ACLK_RGA 205
  80. #define ACLK_PERI 210
  81. #define ACLK_VOP 211
  82. #define ACLK_GMAC 212
  83. #define ACLK_GPU 213
  84. /* pclk gates */
  85. #define PCLK_SARADC 318
  86. #define PCLK_WDT 319
  87. #define PCLK_GPIO0 320
  88. #define PCLK_GPIO1 321
  89. #define PCLK_GPIO2 322
  90. #define PCLK_GPIO3 323
  91. #define PCLK_VIO_H2P 324
  92. #define PCLK_MIPI 325
  93. #define PCLK_EFUSE 326
  94. #define PCLK_HDMI 327
  95. #define PCLK_ACODEC 328
  96. #define PCLK_GRF 329
  97. #define PCLK_I2C0 332
  98. #define PCLK_I2C1 333
  99. #define PCLK_I2C2 334
  100. #define PCLK_I2C3 335
  101. #define PCLK_SPI0 338
  102. #define PCLK_UART0 341
  103. #define PCLK_UART1 342
  104. #define PCLK_UART2 343
  105. #define PCLK_TSADC 344
  106. #define PCLK_PWM 350
  107. #define PCLK_TIMER 353
  108. #define PCLK_CPU 354
  109. #define PCLK_PERI 363
  110. #define PCLK_GMAC 367
  111. #define PCLK_PMU_PRE 368
  112. #define PCLK_SIM_CARD 369
  113. /* hclk gates */
  114. #define HCLK_SPDIF 440
  115. #define HCLK_GPS 441
  116. #define HCLK_USBHOST 442
  117. #define HCLK_I2S_8CH 443
  118. #define HCLK_I2S_2CH 444
  119. #define HCLK_VOP 452
  120. #define HCLK_NANDC 453
  121. #define HCLK_SDMMC 456
  122. #define HCLK_SDIO 457
  123. #define HCLK_EMMC 459
  124. #define HCLK_CPU 460
  125. #define HCLK_VEPU 461
  126. #define HCLK_VDPU 462
  127. #define HCLK_LCDC0 463
  128. #define HCLK_EBC 465
  129. #define HCLK_VIO 466
  130. #define HCLK_RGA 467
  131. #define HCLK_IEP 468
  132. #define HCLK_VIO_H2P 469
  133. #define HCLK_CIF 470
  134. #define HCLK_HOST2 473
  135. #define HCLK_OTG 474
  136. #define HCLK_TSP 475
  137. #define HCLK_CRYPTO 476
  138. #define HCLK_PERI 478
  139. #define CLK_NR_CLKS (HCLK_PERI + 1)
  140. /* soft-reset indices */
  141. #define SRST_CORE0_PO 0
  142. #define SRST_CORE1_PO 1
  143. #define SRST_CORE2_PO 2
  144. #define SRST_CORE3_PO 3
  145. #define SRST_CORE0 4
  146. #define SRST_CORE1 5
  147. #define SRST_CORE2 6
  148. #define SRST_CORE3 7
  149. #define SRST_CORE0_DBG 8
  150. #define SRST_CORE1_DBG 9
  151. #define SRST_CORE2_DBG 10
  152. #define SRST_CORE3_DBG 11
  153. #define SRST_TOPDBG 12
  154. #define SRST_ACLK_CORE 13
  155. #define SRST_STRC_SYS_A 14
  156. #define SRST_L2C 15
  157. #define SRST_CPUSYS_H 18
  158. #define SRST_AHB2APBSYS_H 19
  159. #define SRST_SPDIF 20
  160. #define SRST_INTMEM 21
  161. #define SRST_ROM 22
  162. #define SRST_PERI_NIU 23
  163. #define SRST_I2S_2CH 24
  164. #define SRST_I2S_8CH 25
  165. #define SRST_GPU_PVTM 26
  166. #define SRST_FUNC_PVTM 27
  167. #define SRST_CORE_PVTM 29
  168. #define SRST_EFUSE_P 30
  169. #define SRST_ACODEC_P 31
  170. #define SRST_GPIO0 32
  171. #define SRST_GPIO1 33
  172. #define SRST_GPIO2 34
  173. #define SRST_GPIO3 35
  174. #define SRST_MIPIPHY_P 36
  175. #define SRST_UART0 39
  176. #define SRST_UART1 40
  177. #define SRST_UART2 41
  178. #define SRST_I2C0 43
  179. #define SRST_I2C1 44
  180. #define SRST_I2C2 45
  181. #define SRST_I2C3 46
  182. #define SRST_SFC 47
  183. #define SRST_PWM 48
  184. #define SRST_DAP_PO 50
  185. #define SRST_DAP 51
  186. #define SRST_DAP_SYS 52
  187. #define SRST_CRYPTO 53
  188. #define SRST_GRF 55
  189. #define SRST_GMAC 56
  190. #define SRST_PERIPH_SYS_A 57
  191. #define SRST_PERIPH_SYS_H 58
  192. #define SRST_PERIPH_SYS_P 59
  193. #define SRST_SMART_CARD 60
  194. #define SRST_CPU_PERI 61
  195. #define SRST_EMEM_PERI 62
  196. #define SRST_USB_PERI 63
  197. #define SRST_DMA 64
  198. #define SRST_GPS 67
  199. #define SRST_NANDC 68
  200. #define SRST_USBOTG0 69
  201. #define SRST_OTGC0 71
  202. #define SRST_USBOTG1 72
  203. #define SRST_OTGC1 74
  204. #define SRST_DDRMSCH 79
  205. #define SRST_SDMMC 81
  206. #define SRST_SDIO 82
  207. #define SRST_EMMC 83
  208. #define SRST_SPI 84
  209. #define SRST_WDT 86
  210. #define SRST_SARADC 87
  211. #define SRST_DDRPHY 88
  212. #define SRST_DDRPHY_P 89
  213. #define SRST_DDRCTRL 90
  214. #define SRST_DDRCTRL_P 91
  215. #define SRST_TSP 92
  216. #define SRST_TSP_CLKIN 93
  217. #define SRST_HOST0_ECHI 94
  218. #define SRST_HDMI_P 96
  219. #define SRST_VIO_ARBI_H 97
  220. #define SRST_VIO0_A 98
  221. #define SRST_VIO_BUS_H 99
  222. #define SRST_VOP_A 100
  223. #define SRST_VOP_H 101
  224. #define SRST_VOP_D 102
  225. #define SRST_UTMI0 103
  226. #define SRST_UTMI1 104
  227. #define SRST_USBPOR 105
  228. #define SRST_IEP_A 106
  229. #define SRST_IEP_H 107
  230. #define SRST_RGA_A 108
  231. #define SRST_RGA_H 109
  232. #define SRST_CIF0 110
  233. #define SRST_PMU 111
  234. #define SRST_VCODEC_A 112
  235. #define SRST_VCODEC_H 113
  236. #define SRST_VIO1_A 114
  237. #define SRST_HEVC_CORE 115
  238. #define SRST_VCODEC_NIU_A 116
  239. #define SRST_PMU_NIU_P 117
  240. #define SRST_LCDC0_S 119
  241. #define SRST_GPU 120
  242. #define SRST_GPU_NIU_A 122
  243. #define SRST_EBC_A 123
  244. #define SRST_EBC_H 124
  245. #define SRST_CORE_DBG 128
  246. #define SRST_DBG_P 129
  247. #define SRST_TIMER0 130
  248. #define SRST_TIMER1 131
  249. #define SRST_TIMER2 132
  250. #define SRST_TIMER3 133
  251. #define SRST_TIMER4 134
  252. #define SRST_TIMER5 135
  253. #define SRST_VIO_H2P 136
  254. #define SRST_VIO_MIPI_DSI 137
  255. #endif