r9a06g032-sysctrl.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * R9A06G032 sysctrl IDs
  4. *
  5. * Copyright (C) 2018 Renesas Electronics Europe Limited
  6. *
  7. * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
  8. */
  9. #ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
  10. #define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
  11. #define R9A06G032_CLK_PLL_USB 1
  12. #define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */
  13. #define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
  14. #define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
  15. #define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
  16. #define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */
  17. #define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */
  18. #define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */
  19. #define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
  20. #define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
  21. #define R9A06G032_CLK_25_PG4 26
  22. #define R9A06G032_CLK_25_PG5 27
  23. #define R9A06G032_CLK_25_PG6 28
  24. #define R9A06G032_CLK_25_PG7 29
  25. #define R9A06G032_CLK_25_PG8 30
  26. #define R9A06G032_CLK_ADC 31
  27. #define R9A06G032_CLK_ECAT100 32
  28. #define R9A06G032_CLK_HSR100 33
  29. #define R9A06G032_CLK_I2C0 34
  30. #define R9A06G032_CLK_I2C1 35
  31. #define R9A06G032_CLK_MII_REF 36
  32. #define R9A06G032_CLK_NAND 37
  33. #define R9A06G032_CLK_NOUSBP2_PG6 38
  34. #define R9A06G032_CLK_P1_PG2 39
  35. #define R9A06G032_CLK_P1_PG3 40
  36. #define R9A06G032_CLK_P1_PG4 41
  37. #define R9A06G032_CLK_P4_PG3 42
  38. #define R9A06G032_CLK_P4_PG4 43
  39. #define R9A06G032_CLK_P6_PG1 44
  40. #define R9A06G032_CLK_P6_PG2 45
  41. #define R9A06G032_CLK_P6_PG3 46
  42. #define R9A06G032_CLK_P6_PG4 47
  43. #define R9A06G032_CLK_PCI_USB 48
  44. #define R9A06G032_CLK_QSPI0 49
  45. #define R9A06G032_CLK_QSPI1 50
  46. #define R9A06G032_CLK_RGMII_REF 51
  47. #define R9A06G032_CLK_RMII_REF 52
  48. #define R9A06G032_CLK_SDIO0 53
  49. #define R9A06G032_CLK_SDIO1 54
  50. #define R9A06G032_CLK_SERCOS100 55
  51. #define R9A06G032_CLK_SLCD 56
  52. #define R9A06G032_CLK_SPI0 57
  53. #define R9A06G032_CLK_SPI1 58
  54. #define R9A06G032_CLK_SPI2 59
  55. #define R9A06G032_CLK_SPI3 60
  56. #define R9A06G032_CLK_SPI4 61
  57. #define R9A06G032_CLK_SPI5 62
  58. #define R9A06G032_CLK_SWITCH 63
  59. #define R9A06G032_HCLK_ECAT125 65
  60. #define R9A06G032_HCLK_PINCONFIG 66
  61. #define R9A06G032_HCLK_SERCOS 67
  62. #define R9A06G032_HCLK_SGPIO2 68
  63. #define R9A06G032_HCLK_SGPIO3 69
  64. #define R9A06G032_HCLK_SGPIO4 70
  65. #define R9A06G032_HCLK_TIMER0 71
  66. #define R9A06G032_HCLK_TIMER1 72
  67. #define R9A06G032_HCLK_USBF 73
  68. #define R9A06G032_HCLK_USBH 74
  69. #define R9A06G032_HCLK_USBPM 75
  70. #define R9A06G032_CLK_48_PG_F 76
  71. #define R9A06G032_CLK_48_PG4 77
  72. #define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
  73. #define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
  74. #define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
  75. #define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
  76. #define R9A06G032_HCLK_CAN0 85
  77. #define R9A06G032_HCLK_CAN1 86
  78. #define R9A06G032_HCLK_DELTASIGMA 87
  79. #define R9A06G032_HCLK_PWMPTO 88
  80. #define R9A06G032_HCLK_RSV 89
  81. #define R9A06G032_HCLK_SGPIO0 90
  82. #define R9A06G032_HCLK_SGPIO1 91
  83. #define R9A06G032_RTOS_MDC 92
  84. #define R9A06G032_CLK_CM3 93
  85. #define R9A06G032_CLK_DDRC 94
  86. #define R9A06G032_CLK_ECAT25 95
  87. #define R9A06G032_CLK_HSR50 96
  88. #define R9A06G032_CLK_HW_RTOS 97
  89. #define R9A06G032_CLK_SERCOS50 98
  90. #define R9A06G032_HCLK_ADC 99
  91. #define R9A06G032_HCLK_CM3 100
  92. #define R9A06G032_HCLK_CRYPTO_EIP150 101
  93. #define R9A06G032_HCLK_CRYPTO_EIP93 102
  94. #define R9A06G032_HCLK_DDRC 103
  95. #define R9A06G032_HCLK_DMA0 104
  96. #define R9A06G032_HCLK_DMA1 105
  97. #define R9A06G032_HCLK_GMAC0 106
  98. #define R9A06G032_HCLK_GMAC1 107
  99. #define R9A06G032_HCLK_GPIO0 108
  100. #define R9A06G032_HCLK_GPIO1 109
  101. #define R9A06G032_HCLK_GPIO2 110
  102. #define R9A06G032_HCLK_HSR 111
  103. #define R9A06G032_HCLK_I2C0 112
  104. #define R9A06G032_HCLK_I2C1 113
  105. #define R9A06G032_HCLK_LCD 114
  106. #define R9A06G032_HCLK_MSEBI_M 115
  107. #define R9A06G032_HCLK_MSEBI_S 116
  108. #define R9A06G032_HCLK_NAND 117
  109. #define R9A06G032_HCLK_PG_I 118
  110. #define R9A06G032_HCLK_PG19 119
  111. #define R9A06G032_HCLK_PG20 120
  112. #define R9A06G032_HCLK_PG3 121
  113. #define R9A06G032_HCLK_PG4 122
  114. #define R9A06G032_HCLK_QSPI0 123
  115. #define R9A06G032_HCLK_QSPI1 124
  116. #define R9A06G032_HCLK_ROM 125
  117. #define R9A06G032_HCLK_RTC 126
  118. #define R9A06G032_HCLK_SDIO0 127
  119. #define R9A06G032_HCLK_SDIO1 128
  120. #define R9A06G032_HCLK_SEMAP 129
  121. #define R9A06G032_HCLK_SPI0 130
  122. #define R9A06G032_HCLK_SPI1 131
  123. #define R9A06G032_HCLK_SPI2 132
  124. #define R9A06G032_HCLK_SPI3 133
  125. #define R9A06G032_HCLK_SPI4 134
  126. #define R9A06G032_HCLK_SPI5 135
  127. #define R9A06G032_HCLK_SWITCH 136
  128. #define R9A06G032_HCLK_SWITCH_RG 137
  129. #define R9A06G032_HCLK_UART0 138
  130. #define R9A06G032_HCLK_UART1 139
  131. #define R9A06G032_HCLK_UART2 140
  132. #define R9A06G032_HCLK_UART3 141
  133. #define R9A06G032_HCLK_UART4 142
  134. #define R9A06G032_HCLK_UART5 143
  135. #define R9A06G032_HCLK_UART6 144
  136. #define R9A06G032_HCLK_UART7 145
  137. #define R9A06G032_CLK_UART0 146
  138. #define R9A06G032_CLK_UART1 147
  139. #define R9A06G032_CLK_UART2 148
  140. #define R9A06G032_CLK_UART3 149
  141. #define R9A06G032_CLK_UART4 150
  142. #define R9A06G032_CLK_UART5 151
  143. #define R9A06G032_CLK_UART6 152
  144. #define R9A06G032_CLK_UART7 153
  145. #endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */