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- /* SPDX-License-Identifier: GPL-2.0+
- *
- * Copyright (C) 2020 Renesas Electronics Corp.
- */
- #ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
- #define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
- #include <dt-bindings/clock/renesas-cpg-mssr.h>
- /* r8a7742 CPG Core Clocks */
- #define R8A7742_CLK_Z 0
- #define R8A7742_CLK_Z2 1
- #define R8A7742_CLK_ZG 2
- #define R8A7742_CLK_ZTR 3
- #define R8A7742_CLK_ZTRD2 4
- #define R8A7742_CLK_ZT 5
- #define R8A7742_CLK_ZX 6
- #define R8A7742_CLK_ZS 7
- #define R8A7742_CLK_HP 8
- #define R8A7742_CLK_B 9
- #define R8A7742_CLK_LB 10
- #define R8A7742_CLK_P 11
- #define R8A7742_CLK_CL 12
- #define R8A7742_CLK_M2 13
- #define R8A7742_CLK_ZB3 14
- #define R8A7742_CLK_ZB3D2 15
- #define R8A7742_CLK_DDR 16
- #define R8A7742_CLK_SDH 17
- #define R8A7742_CLK_SD0 18
- #define R8A7742_CLK_SD1 19
- #define R8A7742_CLK_SD2 20
- #define R8A7742_CLK_SD3 21
- #define R8A7742_CLK_MMC0 22
- #define R8A7742_CLK_MMC1 23
- #define R8A7742_CLK_MP 24
- #define R8A7742_CLK_QSPI 25
- #define R8A7742_CLK_CP 26
- #define R8A7742_CLK_RCAN 27
- #define R8A7742_CLK_R 28
- #define R8A7742_CLK_OSC 29
- #endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */
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