qcom,gcc-sdm660.h 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2018, Craig Tatlor.
  5. */
  6. #ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
  7. #define _DT_BINDINGS_CLK_MSM_GCC_660_H
  8. #define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
  9. #define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
  10. #define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
  11. #define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
  12. #define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
  13. #define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
  14. #define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
  15. #define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
  16. #define BLSP1_UART1_APPS_CLK_SRC 8
  17. #define BLSP1_UART2_APPS_CLK_SRC 9
  18. #define BLSP2_QUP1_I2C_APPS_CLK_SRC 10
  19. #define BLSP2_QUP1_SPI_APPS_CLK_SRC 11
  20. #define BLSP2_QUP2_I2C_APPS_CLK_SRC 12
  21. #define BLSP2_QUP2_SPI_APPS_CLK_SRC 13
  22. #define BLSP2_QUP3_I2C_APPS_CLK_SRC 14
  23. #define BLSP2_QUP3_SPI_APPS_CLK_SRC 15
  24. #define BLSP2_QUP4_I2C_APPS_CLK_SRC 16
  25. #define BLSP2_QUP4_SPI_APPS_CLK_SRC 17
  26. #define BLSP2_UART1_APPS_CLK_SRC 18
  27. #define BLSP2_UART2_APPS_CLK_SRC 19
  28. #define GCC_AGGRE2_UFS_AXI_CLK 20
  29. #define GCC_AGGRE2_USB3_AXI_CLK 21
  30. #define GCC_BIMC_GFX_CLK 22
  31. #define GCC_BIMC_HMSS_AXI_CLK 23
  32. #define GCC_BIMC_MSS_Q6_AXI_CLK 24
  33. #define GCC_BLSP1_AHB_CLK 25
  34. #define GCC_BLSP1_QUP1_I2C_APPS_CLK 26
  35. #define GCC_BLSP1_QUP1_SPI_APPS_CLK 27
  36. #define GCC_BLSP1_QUP2_I2C_APPS_CLK 28
  37. #define GCC_BLSP1_QUP2_SPI_APPS_CLK 29
  38. #define GCC_BLSP1_QUP3_I2C_APPS_CLK 30
  39. #define GCC_BLSP1_QUP3_SPI_APPS_CLK 31
  40. #define GCC_BLSP1_QUP4_I2C_APPS_CLK 32
  41. #define GCC_BLSP1_QUP4_SPI_APPS_CLK 33
  42. #define GCC_BLSP1_UART1_APPS_CLK 34
  43. #define GCC_BLSP1_UART2_APPS_CLK 35
  44. #define GCC_BLSP2_AHB_CLK 36
  45. #define GCC_BLSP2_QUP1_I2C_APPS_CLK 37
  46. #define GCC_BLSP2_QUP1_SPI_APPS_CLK 38
  47. #define GCC_BLSP2_QUP2_I2C_APPS_CLK 39
  48. #define GCC_BLSP2_QUP2_SPI_APPS_CLK 40
  49. #define GCC_BLSP2_QUP3_I2C_APPS_CLK 41
  50. #define GCC_BLSP2_QUP3_SPI_APPS_CLK 42
  51. #define GCC_BLSP2_QUP4_I2C_APPS_CLK 43
  52. #define GCC_BLSP2_QUP4_SPI_APPS_CLK 44
  53. #define GCC_BLSP2_UART1_APPS_CLK 45
  54. #define GCC_BLSP2_UART2_APPS_CLK 46
  55. #define GCC_BOOT_ROM_AHB_CLK 47
  56. #define GCC_CFG_NOC_USB2_AXI_CLK 48
  57. #define GCC_CFG_NOC_USB3_AXI_CLK 49
  58. #define GCC_DCC_AHB_CLK 50
  59. #define GCC_GP1_CLK 51
  60. #define GCC_GP2_CLK 52
  61. #define GCC_GP3_CLK 53
  62. #define GCC_GPU_BIMC_GFX_CLK 54
  63. #define GCC_GPU_CFG_AHB_CLK 55
  64. #define GCC_GPU_GPLL0_CLK 56
  65. #define GCC_GPU_GPLL0_DIV_CLK 57
  66. #define GCC_HMSS_DVM_BUS_CLK 58
  67. #define GCC_HMSS_RBCPR_CLK 59
  68. #define GCC_MMSS_GPLL0_CLK 60
  69. #define GCC_MMSS_GPLL0_DIV_CLK 61
  70. #define GCC_MMSS_NOC_CFG_AHB_CLK 62
  71. #define GCC_MMSS_SYS_NOC_AXI_CLK 63
  72. #define GCC_MSS_CFG_AHB_CLK 64
  73. #define GCC_MSS_GPLL0_DIV_CLK 65
  74. #define GCC_MSS_MNOC_BIMC_AXI_CLK 66
  75. #define GCC_MSS_Q6_BIMC_AXI_CLK 67
  76. #define GCC_MSS_SNOC_AXI_CLK 68
  77. #define GCC_PDM2_CLK 69
  78. #define GCC_PDM_AHB_CLK 70
  79. #define GCC_PRNG_AHB_CLK 71
  80. #define GCC_QSPI_AHB_CLK 72
  81. #define GCC_QSPI_SER_CLK 73
  82. #define GCC_SDCC1_AHB_CLK 74
  83. #define GCC_SDCC1_APPS_CLK 75
  84. #define GCC_SDCC1_ICE_CORE_CLK 76
  85. #define GCC_SDCC2_AHB_CLK 77
  86. #define GCC_SDCC2_APPS_CLK 78
  87. #define GCC_UFS_AHB_CLK 79
  88. #define GCC_UFS_AXI_CLK 80
  89. #define GCC_UFS_CLKREF_CLK 81
  90. #define GCC_UFS_ICE_CORE_CLK 82
  91. #define GCC_UFS_PHY_AUX_CLK 83
  92. #define GCC_UFS_RX_SYMBOL_0_CLK 84
  93. #define GCC_UFS_RX_SYMBOL_1_CLK 85
  94. #define GCC_UFS_TX_SYMBOL_0_CLK 86
  95. #define GCC_UFS_UNIPRO_CORE_CLK 87
  96. #define GCC_USB20_MASTER_CLK 88
  97. #define GCC_USB20_MOCK_UTMI_CLK 89
  98. #define GCC_USB20_SLEEP_CLK 90
  99. #define GCC_USB30_MASTER_CLK 91
  100. #define GCC_USB30_MOCK_UTMI_CLK 92
  101. #define GCC_USB30_SLEEP_CLK 93
  102. #define GCC_USB3_CLKREF_CLK 94
  103. #define GCC_USB3_PHY_AUX_CLK 95
  104. #define GCC_USB3_PHY_PIPE_CLK 96
  105. #define GCC_USB_PHY_CFG_AHB2PHY_CLK 97
  106. #define GP1_CLK_SRC 98
  107. #define GP2_CLK_SRC 99
  108. #define GP3_CLK_SRC 100
  109. #define GPLL0 101
  110. #define GPLL0_EARLY 102
  111. #define GPLL1 103
  112. #define GPLL1_EARLY 104
  113. #define GPLL4 105
  114. #define GPLL4_EARLY 106
  115. #define HMSS_GPLL0_CLK_SRC 107
  116. #define HMSS_GPLL4_CLK_SRC 108
  117. #define HMSS_RBCPR_CLK_SRC 109
  118. #define PDM2_CLK_SRC 110
  119. #define QSPI_SER_CLK_SRC 111
  120. #define SDCC1_APPS_CLK_SRC 112
  121. #define SDCC1_ICE_CORE_CLK_SRC 113
  122. #define SDCC2_APPS_CLK_SRC 114
  123. #define UFS_AXI_CLK_SRC 115
  124. #define UFS_ICE_CORE_CLK_SRC 116
  125. #define UFS_PHY_AUX_CLK_SRC 117
  126. #define UFS_UNIPRO_CORE_CLK_SRC 118
  127. #define USB20_MASTER_CLK_SRC 119
  128. #define USB20_MOCK_UTMI_CLK_SRC 120
  129. #define USB30_MASTER_CLK_SRC 121
  130. #define USB30_MOCK_UTMI_CLK_SRC 122
  131. #define USB3_PHY_AUX_CLK_SRC 123
  132. #define GPLL0_OUT_MSSCC 124
  133. #define GCC_UFS_AXI_HW_CTL_CLK 125
  134. #define GCC_UFS_ICE_CORE_HW_CTL_CLK 126
  135. #define GCC_UFS_PHY_AUX_HW_CTL_CLK 127
  136. #define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128
  137. #define GCC_RX0_USB2_CLKREF_CLK 129
  138. #define GCC_RX1_USB2_CLKREF_CLK 130
  139. #define PCIE_0_GDSC 0
  140. #define UFS_GDSC 1
  141. #define USB_30_GDSC 2
  142. #define GCC_QUSB2PHY_PRIM_BCR 0
  143. #define GCC_QUSB2PHY_SEC_BCR 1
  144. #define GCC_UFS_BCR 2
  145. #define GCC_USB3_DP_PHY_BCR 3
  146. #define GCC_USB3_PHY_BCR 4
  147. #define GCC_USB3PHY_PHY_BCR 5
  148. #define GCC_USB_20_BCR 6
  149. #define GCC_USB_30_BCR 7
  150. #define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
  151. #define GCC_MSS_RESTART 9
  152. #endif