qcom,gcc-msm8960.h 8.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2013, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H
  6. #define _DT_BINDINGS_CLK_MSM_GCC_8960_H
  7. #define AFAB_CLK_SRC 0
  8. #define AFAB_CORE_CLK 1
  9. #define SFAB_MSS_Q6_SW_A_CLK 2
  10. #define SFAB_MSS_Q6_FW_A_CLK 3
  11. #define QDSS_STM_CLK 4
  12. #define SCSS_A_CLK 5
  13. #define SCSS_H_CLK 6
  14. #define SCSS_XO_SRC_CLK 7
  15. #define AFAB_EBI1_CH0_A_CLK 8
  16. #define AFAB_EBI1_CH1_A_CLK 9
  17. #define AFAB_AXI_S0_FCLK 10
  18. #define AFAB_AXI_S1_FCLK 11
  19. #define AFAB_AXI_S2_FCLK 12
  20. #define AFAB_AXI_S3_FCLK 13
  21. #define AFAB_AXI_S4_FCLK 14
  22. #define SFAB_CORE_CLK 15
  23. #define SFAB_AXI_S0_FCLK 16
  24. #define SFAB_AXI_S1_FCLK 17
  25. #define SFAB_AXI_S2_FCLK 18
  26. #define SFAB_AXI_S3_FCLK 19
  27. #define SFAB_AXI_S4_FCLK 20
  28. #define SFAB_AHB_S0_FCLK 21
  29. #define SFAB_AHB_S1_FCLK 22
  30. #define SFAB_AHB_S2_FCLK 23
  31. #define SFAB_AHB_S3_FCLK 24
  32. #define SFAB_AHB_S4_FCLK 25
  33. #define SFAB_AHB_S5_FCLK 26
  34. #define SFAB_AHB_S6_FCLK 27
  35. #define SFAB_AHB_S7_FCLK 28
  36. #define QDSS_AT_CLK_SRC 29
  37. #define QDSS_AT_CLK 30
  38. #define QDSS_TRACECLKIN_CLK_SRC 31
  39. #define QDSS_TRACECLKIN_CLK 32
  40. #define QDSS_TSCTR_CLK_SRC 33
  41. #define QDSS_TSCTR_CLK 34
  42. #define SFAB_ADM0_M0_A_CLK 35
  43. #define SFAB_ADM0_M1_A_CLK 36
  44. #define SFAB_ADM0_M2_H_CLK 37
  45. #define ADM0_CLK 38
  46. #define ADM0_PBUS_CLK 39
  47. #define MSS_XPU_CLK 40
  48. #define IMEM0_A_CLK 41
  49. #define QDSS_H_CLK 42
  50. #define PCIE_A_CLK 43
  51. #define PCIE_AUX_CLK 44
  52. #define PCIE_PHY_REF_CLK 45
  53. #define PCIE_H_CLK 46
  54. #define SFAB_CLK_SRC 47
  55. #define MAHB0_CLK 48
  56. #define Q6SW_CLK_SRC 49
  57. #define Q6SW_CLK 50
  58. #define Q6FW_CLK_SRC 51
  59. #define Q6FW_CLK 52
  60. #define SFAB_MSS_M_A_CLK 53
  61. #define SFAB_USB3_M_A_CLK 54
  62. #define SFAB_LPASS_Q6_A_CLK 55
  63. #define SFAB_AFAB_M_A_CLK 56
  64. #define AFAB_SFAB_M0_A_CLK 57
  65. #define AFAB_SFAB_M1_A_CLK 58
  66. #define SFAB_SATA_S_H_CLK 59
  67. #define DFAB_CLK_SRC 60
  68. #define DFAB_CLK 61
  69. #define SFAB_DFAB_M_A_CLK 62
  70. #define DFAB_SFAB_M_A_CLK 63
  71. #define DFAB_SWAY0_H_CLK 64
  72. #define DFAB_SWAY1_H_CLK 65
  73. #define DFAB_ARB0_H_CLK 66
  74. #define DFAB_ARB1_H_CLK 67
  75. #define PPSS_H_CLK 68
  76. #define PPSS_PROC_CLK 69
  77. #define PPSS_TIMER0_CLK 70
  78. #define PPSS_TIMER1_CLK 71
  79. #define PMEM_A_CLK 72
  80. #define DMA_BAM_H_CLK 73
  81. #define SIC_H_CLK 74
  82. #define SPS_TIC_H_CLK 75
  83. #define SLIMBUS_H_CLK 76
  84. #define SLIMBUS_XO_SRC_CLK 77
  85. #define CFPB_2X_CLK_SRC 78
  86. #define CFPB_CLK 79
  87. #define CFPB0_H_CLK 80
  88. #define CFPB1_H_CLK 81
  89. #define CFPB2_H_CLK 82
  90. #define SFAB_CFPB_M_H_CLK 83
  91. #define CFPB_MASTER_H_CLK 84
  92. #define SFAB_CFPB_S_H_CLK 85
  93. #define CFPB_SPLITTER_H_CLK 86
  94. #define TSIF_H_CLK 87
  95. #define TSIF_INACTIVITY_TIMERS_CLK 88
  96. #define TSIF_REF_SRC 89
  97. #define TSIF_REF_CLK 90
  98. #define CE1_H_CLK 91
  99. #define CE1_CORE_CLK 92
  100. #define CE1_SLEEP_CLK 93
  101. #define CE2_H_CLK 94
  102. #define CE2_CORE_CLK 95
  103. #define SFPB_H_CLK_SRC 97
  104. #define SFPB_H_CLK 98
  105. #define SFAB_SFPB_M_H_CLK 99
  106. #define SFAB_SFPB_S_H_CLK 100
  107. #define RPM_PROC_CLK 101
  108. #define RPM_BUS_H_CLK 102
  109. #define RPM_SLEEP_CLK 103
  110. #define RPM_TIMER_CLK 104
  111. #define RPM_MSG_RAM_H_CLK 105
  112. #define PMIC_ARB0_H_CLK 106
  113. #define PMIC_ARB1_H_CLK 107
  114. #define PMIC_SSBI2_SRC 108
  115. #define PMIC_SSBI2_CLK 109
  116. #define SDC1_H_CLK 110
  117. #define SDC2_H_CLK 111
  118. #define SDC3_H_CLK 112
  119. #define SDC4_H_CLK 113
  120. #define SDC5_H_CLK 114
  121. #define SDC1_SRC 115
  122. #define SDC2_SRC 116
  123. #define SDC3_SRC 117
  124. #define SDC4_SRC 118
  125. #define SDC5_SRC 119
  126. #define SDC1_CLK 120
  127. #define SDC2_CLK 121
  128. #define SDC3_CLK 122
  129. #define SDC4_CLK 123
  130. #define SDC5_CLK 124
  131. #define DFAB_A2_H_CLK 125
  132. #define USB_HS1_H_CLK 126
  133. #define USB_HS1_XCVR_SRC 127
  134. #define USB_HS1_XCVR_CLK 128
  135. #define USB_HSIC_H_CLK 129
  136. #define USB_HSIC_XCVR_FS_SRC 130
  137. #define USB_HSIC_XCVR_FS_CLK 131
  138. #define USB_HSIC_SYSTEM_CLK_SRC 132
  139. #define USB_HSIC_SYSTEM_CLK 133
  140. #define CFPB0_C0_H_CLK 134
  141. #define CFPB0_C1_H_CLK 135
  142. #define CFPB0_D0_H_CLK 136
  143. #define CFPB0_D1_H_CLK 137
  144. #define USB_FS1_H_CLK 138
  145. #define USB_FS1_XCVR_FS_SRC 139
  146. #define USB_FS1_XCVR_FS_CLK 140
  147. #define USB_FS1_SYSTEM_CLK 141
  148. #define USB_FS2_H_CLK 142
  149. #define USB_FS2_XCVR_FS_SRC 143
  150. #define USB_FS2_XCVR_FS_CLK 144
  151. #define USB_FS2_SYSTEM_CLK 145
  152. #define GSBI_COMMON_SIM_SRC 146
  153. #define GSBI1_H_CLK 147
  154. #define GSBI2_H_CLK 148
  155. #define GSBI3_H_CLK 149
  156. #define GSBI4_H_CLK 150
  157. #define GSBI5_H_CLK 151
  158. #define GSBI6_H_CLK 152
  159. #define GSBI7_H_CLK 153
  160. #define GSBI8_H_CLK 154
  161. #define GSBI9_H_CLK 155
  162. #define GSBI10_H_CLK 156
  163. #define GSBI11_H_CLK 157
  164. #define GSBI12_H_CLK 158
  165. #define GSBI1_UART_SRC 159
  166. #define GSBI1_UART_CLK 160
  167. #define GSBI2_UART_SRC 161
  168. #define GSBI2_UART_CLK 162
  169. #define GSBI3_UART_SRC 163
  170. #define GSBI3_UART_CLK 164
  171. #define GSBI4_UART_SRC 165
  172. #define GSBI4_UART_CLK 166
  173. #define GSBI5_UART_SRC 167
  174. #define GSBI5_UART_CLK 168
  175. #define GSBI6_UART_SRC 169
  176. #define GSBI6_UART_CLK 170
  177. #define GSBI7_UART_SRC 171
  178. #define GSBI7_UART_CLK 172
  179. #define GSBI8_UART_SRC 173
  180. #define GSBI8_UART_CLK 174
  181. #define GSBI9_UART_SRC 175
  182. #define GSBI9_UART_CLK 176
  183. #define GSBI10_UART_SRC 177
  184. #define GSBI10_UART_CLK 178
  185. #define GSBI11_UART_SRC 179
  186. #define GSBI11_UART_CLK 180
  187. #define GSBI12_UART_SRC 181
  188. #define GSBI12_UART_CLK 182
  189. #define GSBI1_QUP_SRC 183
  190. #define GSBI1_QUP_CLK 184
  191. #define GSBI2_QUP_SRC 185
  192. #define GSBI2_QUP_CLK 186
  193. #define GSBI3_QUP_SRC 187
  194. #define GSBI3_QUP_CLK 188
  195. #define GSBI4_QUP_SRC 189
  196. #define GSBI4_QUP_CLK 190
  197. #define GSBI5_QUP_SRC 191
  198. #define GSBI5_QUP_CLK 192
  199. #define GSBI6_QUP_SRC 193
  200. #define GSBI6_QUP_CLK 194
  201. #define GSBI7_QUP_SRC 195
  202. #define GSBI7_QUP_CLK 196
  203. #define GSBI8_QUP_SRC 197
  204. #define GSBI8_QUP_CLK 198
  205. #define GSBI9_QUP_SRC 199
  206. #define GSBI9_QUP_CLK 200
  207. #define GSBI10_QUP_SRC 201
  208. #define GSBI10_QUP_CLK 202
  209. #define GSBI11_QUP_SRC 203
  210. #define GSBI11_QUP_CLK 204
  211. #define GSBI12_QUP_SRC 205
  212. #define GSBI12_QUP_CLK 206
  213. #define GSBI1_SIM_CLK 207
  214. #define GSBI2_SIM_CLK 208
  215. #define GSBI3_SIM_CLK 209
  216. #define GSBI4_SIM_CLK 210
  217. #define GSBI5_SIM_CLK 211
  218. #define GSBI6_SIM_CLK 212
  219. #define GSBI7_SIM_CLK 213
  220. #define GSBI8_SIM_CLK 214
  221. #define GSBI9_SIM_CLK 215
  222. #define GSBI10_SIM_CLK 216
  223. #define GSBI11_SIM_CLK 217
  224. #define GSBI12_SIM_CLK 218
  225. #define USB_HSIC_HSIC_CLK_SRC 219
  226. #define USB_HSIC_HSIC_CLK 220
  227. #define USB_HSIC_HSIO_CAL_CLK 221
  228. #define SPDM_CFG_H_CLK 222
  229. #define SPDM_MSTR_H_CLK 223
  230. #define SPDM_FF_CLK_SRC 224
  231. #define SPDM_FF_CLK 225
  232. #define SEC_CTRL_CLK 226
  233. #define SEC_CTRL_ACC_CLK_SRC 227
  234. #define SEC_CTRL_ACC_CLK 228
  235. #define TLMM_H_CLK 229
  236. #define TLMM_CLK 230
  237. #define SFAB_MSS_S_H_CLK 231
  238. #define MSS_SLP_CLK 232
  239. #define MSS_Q6SW_JTAG_CLK 233
  240. #define MSS_Q6FW_JTAG_CLK 234
  241. #define MSS_S_H_CLK 235
  242. #define MSS_CXO_SRC_CLK 236
  243. #define SATA_H_CLK 237
  244. #define SATA_CLK_SRC 238
  245. #define SATA_RXOOB_CLK 239
  246. #define SATA_PMALIVE_CLK 240
  247. #define SATA_PHY_REF_CLK 241
  248. #define TSSC_CLK_SRC 242
  249. #define TSSC_CLK 243
  250. #define PDM_SRC 244
  251. #define PDM_CLK 245
  252. #define GP0_SRC 246
  253. #define GP0_CLK 247
  254. #define GP1_SRC 248
  255. #define GP1_CLK 249
  256. #define GP2_SRC 250
  257. #define GP2_CLK 251
  258. #define MPM_CLK 252
  259. #define EBI1_CLK_SRC 253
  260. #define EBI1_CH0_CLK 254
  261. #define EBI1_CH1_CLK 255
  262. #define EBI1_2X_CLK 256
  263. #define EBI1_CH0_DQ_CLK 257
  264. #define EBI1_CH1_DQ_CLK 258
  265. #define EBI1_CH0_CA_CLK 259
  266. #define EBI1_CH1_CA_CLK 260
  267. #define EBI1_XO_CLK 261
  268. #define SFAB_SMPSS_S_H_CLK 262
  269. #define PRNG_SRC 263
  270. #define PRNG_CLK 264
  271. #define PXO_SRC 265
  272. #define LPASS_CXO_CLK 266
  273. #define LPASS_PXO_CLK 267
  274. #define SPDM_CY_PORT0_CLK 268
  275. #define SPDM_CY_PORT1_CLK 269
  276. #define SPDM_CY_PORT2_CLK 270
  277. #define SPDM_CY_PORT3_CLK 271
  278. #define SPDM_CY_PORT4_CLK 272
  279. #define SPDM_CY_PORT5_CLK 273
  280. #define SPDM_CY_PORT6_CLK 274
  281. #define SPDM_CY_PORT7_CLK 275
  282. #define PLL0 276
  283. #define PLL0_VOTE 277
  284. #define PLL3 278
  285. #define PLL3_VOTE 279
  286. #define PLL4_VOTE 280
  287. #define PLL5 281
  288. #define PLL5_VOTE 282
  289. #define PLL6 283
  290. #define PLL6_VOTE 284
  291. #define PLL7_VOTE 285
  292. #define PLL8 286
  293. #define PLL8_VOTE 287
  294. #define PLL9 288
  295. #define PLL10 289
  296. #define PLL11 290
  297. #define PLL12 291
  298. #define PLL13 292
  299. #define PLL14 293
  300. #define PLL14_VOTE 294
  301. #define USB_HS3_H_CLK 295
  302. #define USB_HS3_XCVR_SRC 296
  303. #define USB_HS3_XCVR_CLK 297
  304. #define USB_HS4_H_CLK 298
  305. #define USB_HS4_XCVR_SRC 299
  306. #define USB_HS4_XCVR_CLK 300
  307. #define SATA_PHY_CFG_CLK 301
  308. #define SATA_A_CLK 302
  309. #define CE3_SRC 303
  310. #define CE3_CORE_CLK 304
  311. #define CE3_H_CLK 305
  312. #define PLL16 306
  313. #define PLL17 307
  314. #endif