qcom,gcc-ipq806x.h 8.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
  6. #define _DT_BINDINGS_CLK_GCC_IPQ806X_H
  7. #define AFAB_CLK_SRC 0
  8. #define QDSS_STM_CLK 1
  9. #define SCSS_A_CLK 2
  10. #define SCSS_H_CLK 3
  11. #define AFAB_CORE_CLK 4
  12. #define SCSS_XO_SRC_CLK 5
  13. #define AFAB_EBI1_CH0_A_CLK 6
  14. #define AFAB_EBI1_CH1_A_CLK 7
  15. #define AFAB_AXI_S0_FCLK 8
  16. #define AFAB_AXI_S1_FCLK 9
  17. #define AFAB_AXI_S2_FCLK 10
  18. #define AFAB_AXI_S3_FCLK 11
  19. #define AFAB_AXI_S4_FCLK 12
  20. #define SFAB_CORE_CLK 13
  21. #define SFAB_AXI_S0_FCLK 14
  22. #define SFAB_AXI_S1_FCLK 15
  23. #define SFAB_AXI_S2_FCLK 16
  24. #define SFAB_AXI_S3_FCLK 17
  25. #define SFAB_AXI_S4_FCLK 18
  26. #define SFAB_AXI_S5_FCLK 19
  27. #define SFAB_AHB_S0_FCLK 20
  28. #define SFAB_AHB_S1_FCLK 21
  29. #define SFAB_AHB_S2_FCLK 22
  30. #define SFAB_AHB_S3_FCLK 23
  31. #define SFAB_AHB_S4_FCLK 24
  32. #define SFAB_AHB_S5_FCLK 25
  33. #define SFAB_AHB_S6_FCLK 26
  34. #define SFAB_AHB_S7_FCLK 27
  35. #define QDSS_AT_CLK_SRC 28
  36. #define QDSS_AT_CLK 29
  37. #define QDSS_TRACECLKIN_CLK_SRC 30
  38. #define QDSS_TRACECLKIN_CLK 31
  39. #define QDSS_TSCTR_CLK_SRC 32
  40. #define QDSS_TSCTR_CLK 33
  41. #define SFAB_ADM0_M0_A_CLK 34
  42. #define SFAB_ADM0_M1_A_CLK 35
  43. #define SFAB_ADM0_M2_H_CLK 36
  44. #define ADM0_CLK 37
  45. #define ADM0_PBUS_CLK 38
  46. #define IMEM0_A_CLK 39
  47. #define QDSS_H_CLK 40
  48. #define PCIE_A_CLK 41
  49. #define PCIE_AUX_CLK 42
  50. #define PCIE_H_CLK 43
  51. #define PCIE_PHY_CLK 44
  52. #define SFAB_CLK_SRC 45
  53. #define SFAB_LPASS_Q6_A_CLK 46
  54. #define SFAB_AFAB_M_A_CLK 47
  55. #define AFAB_SFAB_M0_A_CLK 48
  56. #define AFAB_SFAB_M1_A_CLK 49
  57. #define SFAB_SATA_S_H_CLK 50
  58. #define DFAB_CLK_SRC 51
  59. #define DFAB_CLK 52
  60. #define SFAB_DFAB_M_A_CLK 53
  61. #define DFAB_SFAB_M_A_CLK 54
  62. #define DFAB_SWAY0_H_CLK 55
  63. #define DFAB_SWAY1_H_CLK 56
  64. #define DFAB_ARB0_H_CLK 57
  65. #define DFAB_ARB1_H_CLK 58
  66. #define PPSS_H_CLK 59
  67. #define PPSS_PROC_CLK 60
  68. #define PPSS_TIMER0_CLK 61
  69. #define PPSS_TIMER1_CLK 62
  70. #define PMEM_A_CLK 63
  71. #define DMA_BAM_H_CLK 64
  72. #define SIC_H_CLK 65
  73. #define SPS_TIC_H_CLK 66
  74. #define CFPB_2X_CLK_SRC 67
  75. #define CFPB_CLK 68
  76. #define CFPB0_H_CLK 69
  77. #define CFPB1_H_CLK 70
  78. #define CFPB2_H_CLK 71
  79. #define SFAB_CFPB_M_H_CLK 72
  80. #define CFPB_MASTER_H_CLK 73
  81. #define SFAB_CFPB_S_H_CLK 74
  82. #define CFPB_SPLITTER_H_CLK 75
  83. #define TSIF_H_CLK 76
  84. #define TSIF_INACTIVITY_TIMERS_CLK 77
  85. #define TSIF_REF_SRC 78
  86. #define TSIF_REF_CLK 79
  87. #define CE1_H_CLK 80
  88. #define CE1_CORE_CLK 81
  89. #define CE1_SLEEP_CLK 82
  90. #define CE2_H_CLK 83
  91. #define CE2_CORE_CLK 84
  92. #define SFPB_H_CLK_SRC 85
  93. #define SFPB_H_CLK 86
  94. #define SFAB_SFPB_M_H_CLK 87
  95. #define SFAB_SFPB_S_H_CLK 88
  96. #define RPM_PROC_CLK 89
  97. #define RPM_BUS_H_CLK 90
  98. #define RPM_SLEEP_CLK 91
  99. #define RPM_TIMER_CLK 92
  100. #define RPM_MSG_RAM_H_CLK 93
  101. #define PMIC_ARB0_H_CLK 94
  102. #define PMIC_ARB1_H_CLK 95
  103. #define PMIC_SSBI2_SRC 96
  104. #define PMIC_SSBI2_CLK 97
  105. #define SDC1_H_CLK 98
  106. #define SDC2_H_CLK 99
  107. #define SDC3_H_CLK 100
  108. #define SDC4_H_CLK 101
  109. #define SDC1_SRC 102
  110. #define SDC1_CLK 103
  111. #define SDC2_SRC 104
  112. #define SDC2_CLK 105
  113. #define SDC3_SRC 106
  114. #define SDC3_CLK 107
  115. #define SDC4_SRC 108
  116. #define SDC4_CLK 109
  117. #define USB_HS1_H_CLK 110
  118. #define USB_HS1_XCVR_SRC 111
  119. #define USB_HS1_XCVR_CLK 112
  120. #define USB_HSIC_H_CLK 113
  121. #define USB_HSIC_XCVR_SRC 114
  122. #define USB_HSIC_XCVR_CLK 115
  123. #define USB_HSIC_SYSTEM_CLK_SRC 116
  124. #define USB_HSIC_SYSTEM_CLK 117
  125. #define CFPB0_C0_H_CLK 118
  126. #define CFPB0_D0_H_CLK 119
  127. #define CFPB0_C1_H_CLK 120
  128. #define CFPB0_D1_H_CLK 121
  129. #define USB_FS1_H_CLK 122
  130. #define USB_FS1_XCVR_SRC 123
  131. #define USB_FS1_XCVR_CLK 124
  132. #define USB_FS1_SYSTEM_CLK 125
  133. #define GSBI_COMMON_SIM_SRC 126
  134. #define GSBI1_H_CLK 127
  135. #define GSBI2_H_CLK 128
  136. #define GSBI3_H_CLK 129
  137. #define GSBI4_H_CLK 130
  138. #define GSBI5_H_CLK 131
  139. #define GSBI6_H_CLK 132
  140. #define GSBI7_H_CLK 133
  141. #define GSBI1_QUP_SRC 134
  142. #define GSBI1_QUP_CLK 135
  143. #define GSBI2_QUP_SRC 136
  144. #define GSBI2_QUP_CLK 137
  145. #define GSBI3_QUP_SRC 138
  146. #define GSBI3_QUP_CLK 139
  147. #define GSBI4_QUP_SRC 140
  148. #define GSBI4_QUP_CLK 141
  149. #define GSBI5_QUP_SRC 142
  150. #define GSBI5_QUP_CLK 143
  151. #define GSBI6_QUP_SRC 144
  152. #define GSBI6_QUP_CLK 145
  153. #define GSBI7_QUP_SRC 146
  154. #define GSBI7_QUP_CLK 147
  155. #define GSBI1_UART_SRC 148
  156. #define GSBI1_UART_CLK 149
  157. #define GSBI2_UART_SRC 150
  158. #define GSBI2_UART_CLK 151
  159. #define GSBI3_UART_SRC 152
  160. #define GSBI3_UART_CLK 153
  161. #define GSBI4_UART_SRC 154
  162. #define GSBI4_UART_CLK 155
  163. #define GSBI5_UART_SRC 156
  164. #define GSBI5_UART_CLK 157
  165. #define GSBI6_UART_SRC 158
  166. #define GSBI6_UART_CLK 159
  167. #define GSBI7_UART_SRC 160
  168. #define GSBI7_UART_CLK 161
  169. #define GSBI1_SIM_CLK 162
  170. #define GSBI2_SIM_CLK 163
  171. #define GSBI3_SIM_CLK 164
  172. #define GSBI4_SIM_CLK 165
  173. #define GSBI5_SIM_CLK 166
  174. #define GSBI6_SIM_CLK 167
  175. #define GSBI7_SIM_CLK 168
  176. #define USB_HSIC_HSIC_CLK_SRC 169
  177. #define USB_HSIC_HSIC_CLK 170
  178. #define USB_HSIC_HSIO_CAL_CLK 171
  179. #define SPDM_CFG_H_CLK 172
  180. #define SPDM_MSTR_H_CLK 173
  181. #define SPDM_FF_CLK_SRC 174
  182. #define SPDM_FF_CLK 175
  183. #define SEC_CTRL_CLK 176
  184. #define SEC_CTRL_ACC_CLK_SRC 177
  185. #define SEC_CTRL_ACC_CLK 178
  186. #define TLMM_H_CLK 179
  187. #define TLMM_CLK 180
  188. #define SATA_H_CLK 181
  189. #define SATA_CLK_SRC 182
  190. #define SATA_RXOOB_CLK 183
  191. #define SATA_PMALIVE_CLK 184
  192. #define SATA_PHY_REF_CLK 185
  193. #define SATA_A_CLK 186
  194. #define SATA_PHY_CFG_CLK 187
  195. #define TSSC_CLK_SRC 188
  196. #define TSSC_CLK 189
  197. #define PDM_SRC 190
  198. #define PDM_CLK 191
  199. #define GP0_SRC 192
  200. #define GP0_CLK 193
  201. #define GP1_SRC 194
  202. #define GP1_CLK 195
  203. #define GP2_SRC 196
  204. #define GP2_CLK 197
  205. #define MPM_CLK 198
  206. #define EBI1_CLK_SRC 199
  207. #define EBI1_CH0_CLK 200
  208. #define EBI1_CH1_CLK 201
  209. #define EBI1_2X_CLK 202
  210. #define EBI1_CH0_DQ_CLK 203
  211. #define EBI1_CH1_DQ_CLK 204
  212. #define EBI1_CH0_CA_CLK 205
  213. #define EBI1_CH1_CA_CLK 206
  214. #define EBI1_XO_CLK 207
  215. #define SFAB_SMPSS_S_H_CLK 208
  216. #define PRNG_SRC 209
  217. #define PRNG_CLK 210
  218. #define PXO_SRC 211
  219. #define SPDM_CY_PORT0_CLK 212
  220. #define SPDM_CY_PORT1_CLK 213
  221. #define SPDM_CY_PORT2_CLK 214
  222. #define SPDM_CY_PORT3_CLK 215
  223. #define SPDM_CY_PORT4_CLK 216
  224. #define SPDM_CY_PORT5_CLK 217
  225. #define SPDM_CY_PORT6_CLK 218
  226. #define SPDM_CY_PORT7_CLK 219
  227. #define PLL0 220
  228. #define PLL0_VOTE 221
  229. #define PLL3 222
  230. #define PLL3_VOTE 223
  231. #define PLL4_VOTE 225
  232. #define PLL8 226
  233. #define PLL8_VOTE 227
  234. #define PLL9 228
  235. #define PLL10 229
  236. #define PLL11 230
  237. #define PLL12 231
  238. #define PLL14 232
  239. #define PLL14_VOTE 233
  240. #define PLL18 234
  241. #define CE5_SRC 235
  242. #define CE5_H_CLK 236
  243. #define CE5_CORE_CLK 237
  244. #define CE3_SLEEP_CLK 238
  245. #define SFAB_AHB_S8_FCLK 239
  246. #define SPDM_CY_PORT8_CLK 246
  247. #define PCIE_ALT_REF_SRC 247
  248. #define PCIE_ALT_REF_CLK 248
  249. #define PCIE_1_A_CLK 249
  250. #define PCIE_1_AUX_CLK 250
  251. #define PCIE_1_H_CLK 251
  252. #define PCIE_1_PHY_CLK 252
  253. #define PCIE_1_ALT_REF_SRC 253
  254. #define PCIE_1_ALT_REF_CLK 254
  255. #define PCIE_2_A_CLK 255
  256. #define PCIE_2_AUX_CLK 256
  257. #define PCIE_2_H_CLK 257
  258. #define PCIE_2_PHY_CLK 258
  259. #define PCIE_2_ALT_REF_SRC 259
  260. #define PCIE_2_ALT_REF_CLK 260
  261. #define EBI2_CLK 261
  262. #define USB30_SLEEP_CLK 262
  263. #define USB30_UTMI_SRC 263
  264. #define USB30_0_UTMI_CLK 264
  265. #define USB30_1_UTMI_CLK 265
  266. #define USB30_MASTER_SRC 266
  267. #define USB30_0_MASTER_CLK 267
  268. #define USB30_1_MASTER_CLK 268
  269. #define GMAC_CORE1_CLK_SRC 269
  270. #define GMAC_CORE2_CLK_SRC 270
  271. #define GMAC_CORE3_CLK_SRC 271
  272. #define GMAC_CORE4_CLK_SRC 272
  273. #define GMAC_CORE1_CLK 273
  274. #define GMAC_CORE2_CLK 274
  275. #define GMAC_CORE3_CLK 275
  276. #define GMAC_CORE4_CLK 276
  277. #define UBI32_CORE1_CLK_SRC 277
  278. #define UBI32_CORE2_CLK_SRC 278
  279. #define UBI32_CORE1_CLK 279
  280. #define UBI32_CORE2_CLK 280
  281. #define EBI2_AON_CLK 281
  282. #define NSSTCM_CLK_SRC 282
  283. #define NSSTCM_CLK 283
  284. #endif