qcom,camcc-sdm845.h 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
  6. #define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
  7. /* CAM_CC clock registers */
  8. #define CAM_CC_BPS_AHB_CLK 0
  9. #define CAM_CC_BPS_AREG_CLK 1
  10. #define CAM_CC_BPS_AXI_CLK 2
  11. #define CAM_CC_BPS_CLK 3
  12. #define CAM_CC_BPS_CLK_SRC 4
  13. #define CAM_CC_CAMNOC_ATB_CLK 5
  14. #define CAM_CC_CAMNOC_AXI_CLK 6
  15. #define CAM_CC_CCI_CLK 7
  16. #define CAM_CC_CCI_CLK_SRC 8
  17. #define CAM_CC_CPAS_AHB_CLK 9
  18. #define CAM_CC_CPHY_RX_CLK_SRC 10
  19. #define CAM_CC_CSI0PHYTIMER_CLK 11
  20. #define CAM_CC_CSI0PHYTIMER_CLK_SRC 12
  21. #define CAM_CC_CSI1PHYTIMER_CLK 13
  22. #define CAM_CC_CSI1PHYTIMER_CLK_SRC 14
  23. #define CAM_CC_CSI2PHYTIMER_CLK 15
  24. #define CAM_CC_CSI2PHYTIMER_CLK_SRC 16
  25. #define CAM_CC_CSI3PHYTIMER_CLK 17
  26. #define CAM_CC_CSI3PHYTIMER_CLK_SRC 18
  27. #define CAM_CC_CSIPHY0_CLK 19
  28. #define CAM_CC_CSIPHY1_CLK 20
  29. #define CAM_CC_CSIPHY2_CLK 21
  30. #define CAM_CC_CSIPHY3_CLK 22
  31. #define CAM_CC_FAST_AHB_CLK_SRC 23
  32. #define CAM_CC_FD_CORE_CLK 24
  33. #define CAM_CC_FD_CORE_CLK_SRC 25
  34. #define CAM_CC_FD_CORE_UAR_CLK 26
  35. #define CAM_CC_ICP_APB_CLK 27
  36. #define CAM_CC_ICP_ATB_CLK 28
  37. #define CAM_CC_ICP_CLK 29
  38. #define CAM_CC_ICP_CLK_SRC 30
  39. #define CAM_CC_ICP_CTI_CLK 31
  40. #define CAM_CC_ICP_TS_CLK 32
  41. #define CAM_CC_IFE_0_AXI_CLK 33
  42. #define CAM_CC_IFE_0_CLK 34
  43. #define CAM_CC_IFE_0_CLK_SRC 35
  44. #define CAM_CC_IFE_0_CPHY_RX_CLK 36
  45. #define CAM_CC_IFE_0_CSID_CLK 37
  46. #define CAM_CC_IFE_0_CSID_CLK_SRC 38
  47. #define CAM_CC_IFE_0_DSP_CLK 39
  48. #define CAM_CC_IFE_1_AXI_CLK 40
  49. #define CAM_CC_IFE_1_CLK 41
  50. #define CAM_CC_IFE_1_CLK_SRC 42
  51. #define CAM_CC_IFE_1_CPHY_RX_CLK 43
  52. #define CAM_CC_IFE_1_CSID_CLK 44
  53. #define CAM_CC_IFE_1_CSID_CLK_SRC 45
  54. #define CAM_CC_IFE_1_DSP_CLK 46
  55. #define CAM_CC_IFE_LITE_CLK 47
  56. #define CAM_CC_IFE_LITE_CLK_SRC 48
  57. #define CAM_CC_IFE_LITE_CPHY_RX_CLK 49
  58. #define CAM_CC_IFE_LITE_CSID_CLK 50
  59. #define CAM_CC_IFE_LITE_CSID_CLK_SRC 51
  60. #define CAM_CC_IPE_0_AHB_CLK 52
  61. #define CAM_CC_IPE_0_AREG_CLK 53
  62. #define CAM_CC_IPE_0_AXI_CLK 54
  63. #define CAM_CC_IPE_0_CLK 55
  64. #define CAM_CC_IPE_0_CLK_SRC 56
  65. #define CAM_CC_IPE_1_AHB_CLK 57
  66. #define CAM_CC_IPE_1_AREG_CLK 58
  67. #define CAM_CC_IPE_1_AXI_CLK 59
  68. #define CAM_CC_IPE_1_CLK 60
  69. #define CAM_CC_IPE_1_CLK_SRC 61
  70. #define CAM_CC_JPEG_CLK 62
  71. #define CAM_CC_JPEG_CLK_SRC 63
  72. #define CAM_CC_LRME_CLK 64
  73. #define CAM_CC_LRME_CLK_SRC 65
  74. #define CAM_CC_MCLK0_CLK 66
  75. #define CAM_CC_MCLK0_CLK_SRC 67
  76. #define CAM_CC_MCLK1_CLK 68
  77. #define CAM_CC_MCLK1_CLK_SRC 69
  78. #define CAM_CC_MCLK2_CLK 70
  79. #define CAM_CC_MCLK2_CLK_SRC 71
  80. #define CAM_CC_MCLK3_CLK 72
  81. #define CAM_CC_MCLK3_CLK_SRC 73
  82. #define CAM_CC_PLL0 74
  83. #define CAM_CC_PLL0_OUT_EVEN 75
  84. #define CAM_CC_PLL1 76
  85. #define CAM_CC_PLL1_OUT_EVEN 77
  86. #define CAM_CC_PLL2 78
  87. #define CAM_CC_PLL2_OUT_EVEN 79
  88. #define CAM_CC_PLL3 80
  89. #define CAM_CC_PLL3_OUT_EVEN 81
  90. #define CAM_CC_SLOW_AHB_CLK_SRC 82
  91. #define CAM_CC_SOC_AHB_CLK 83
  92. #define CAM_CC_SYS_TMR_CLK 84
  93. /* CAM_CC Resets */
  94. #define TITAN_CAM_CC_CCI_BCR 0
  95. #define TITAN_CAM_CC_CPAS_BCR 1
  96. #define TITAN_CAM_CC_CSI0PHY_BCR 2
  97. #define TITAN_CAM_CC_CSI1PHY_BCR 3
  98. #define TITAN_CAM_CC_CSI2PHY_BCR 4
  99. #define TITAN_CAM_CC_MCLK0_BCR 5
  100. #define TITAN_CAM_CC_MCLK1_BCR 6
  101. #define TITAN_CAM_CC_MCLK2_BCR 7
  102. #define TITAN_CAM_CC_MCLK3_BCR 8
  103. #define TITAN_CAM_CC_TITAN_TOP_BCR 9
  104. /* CAM_CC GDSCRs */
  105. #define BPS_GDSC 0
  106. #define IPE_0_GDSC 1
  107. #define IPE_1_GDSC 2
  108. #define IFE_0_GDSC 3
  109. #define IFE_1_GDSC 4
  110. #define TITAN_TOP_GDSC 5
  111. #endif