mt8183-clk.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018 MediaTek Inc.
  4. * Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. */
  6. #ifndef _DT_BINDINGS_CLK_MT8183_H
  7. #define _DT_BINDINGS_CLK_MT8183_H
  8. /* APMIXED */
  9. #define CLK_APMIXED_ARMPLL_LL 0
  10. #define CLK_APMIXED_ARMPLL_L 1
  11. #define CLK_APMIXED_CCIPLL 2
  12. #define CLK_APMIXED_MAINPLL 3
  13. #define CLK_APMIXED_UNIV2PLL 4
  14. #define CLK_APMIXED_MSDCPLL 5
  15. #define CLK_APMIXED_MMPLL 6
  16. #define CLK_APMIXED_MFGPLL 7
  17. #define CLK_APMIXED_TVDPLL 8
  18. #define CLK_APMIXED_APLL1 9
  19. #define CLK_APMIXED_APLL2 10
  20. #define CLK_APMIXED_SSUSB_26M 11
  21. #define CLK_APMIXED_APPLL_26M 12
  22. #define CLK_APMIXED_MIPIC0_26M 13
  23. #define CLK_APMIXED_MDPLLGP_26M 14
  24. #define CLK_APMIXED_MMSYS_26M 15
  25. #define CLK_APMIXED_UFS_26M 16
  26. #define CLK_APMIXED_MIPIC1_26M 17
  27. #define CLK_APMIXED_MEMPLL_26M 18
  28. #define CLK_APMIXED_CLKSQ_LVPLL_26M 19
  29. #define CLK_APMIXED_MIPID0_26M 20
  30. #define CLK_APMIXED_MIPID1_26M 21
  31. #define CLK_APMIXED_NR_CLK 22
  32. /* TOPCKGEN */
  33. #define CLK_TOP_MUX_AXI 0
  34. #define CLK_TOP_MUX_MM 1
  35. #define CLK_TOP_MUX_CAM 2
  36. #define CLK_TOP_MUX_MFG 3
  37. #define CLK_TOP_MUX_CAMTG 4
  38. #define CLK_TOP_MUX_UART 5
  39. #define CLK_TOP_MUX_SPI 6
  40. #define CLK_TOP_MUX_MSDC50_0_HCLK 7
  41. #define CLK_TOP_MUX_MSDC50_0 8
  42. #define CLK_TOP_MUX_MSDC30_1 9
  43. #define CLK_TOP_MUX_MSDC30_2 10
  44. #define CLK_TOP_MUX_AUDIO 11
  45. #define CLK_TOP_MUX_AUD_INTBUS 12
  46. #define CLK_TOP_MUX_FPWRAP_ULPOSC 13
  47. #define CLK_TOP_MUX_SCP 14
  48. #define CLK_TOP_MUX_ATB 15
  49. #define CLK_TOP_MUX_SSPM 16
  50. #define CLK_TOP_MUX_DPI0 17
  51. #define CLK_TOP_MUX_SCAM 18
  52. #define CLK_TOP_MUX_AUD_1 19
  53. #define CLK_TOP_MUX_AUD_2 20
  54. #define CLK_TOP_MUX_DISP_PWM 21
  55. #define CLK_TOP_MUX_SSUSB_TOP_XHCI 22
  56. #define CLK_TOP_MUX_USB_TOP 23
  57. #define CLK_TOP_MUX_SPM 24
  58. #define CLK_TOP_MUX_I2C 25
  59. #define CLK_TOP_MUX_F52M_MFG 26
  60. #define CLK_TOP_MUX_SENINF 27
  61. #define CLK_TOP_MUX_DXCC 28
  62. #define CLK_TOP_MUX_CAMTG2 29
  63. #define CLK_TOP_MUX_AUD_ENG1 30
  64. #define CLK_TOP_MUX_AUD_ENG2 31
  65. #define CLK_TOP_MUX_FAES_UFSFDE 32
  66. #define CLK_TOP_MUX_FUFS 33
  67. #define CLK_TOP_MUX_IMG 34
  68. #define CLK_TOP_MUX_DSP 35
  69. #define CLK_TOP_MUX_DSP1 36
  70. #define CLK_TOP_MUX_DSP2 37
  71. #define CLK_TOP_MUX_IPU_IF 38
  72. #define CLK_TOP_MUX_CAMTG3 39
  73. #define CLK_TOP_MUX_CAMTG4 40
  74. #define CLK_TOP_MUX_PMICSPI 41
  75. #define CLK_TOP_SYSPLL_CK 42
  76. #define CLK_TOP_SYSPLL_D2 43
  77. #define CLK_TOP_SYSPLL_D3 44
  78. #define CLK_TOP_SYSPLL_D5 45
  79. #define CLK_TOP_SYSPLL_D7 46
  80. #define CLK_TOP_SYSPLL_D2_D2 47
  81. #define CLK_TOP_SYSPLL_D2_D4 48
  82. #define CLK_TOP_SYSPLL_D2_D8 49
  83. #define CLK_TOP_SYSPLL_D2_D16 50
  84. #define CLK_TOP_SYSPLL_D3_D2 51
  85. #define CLK_TOP_SYSPLL_D3_D4 52
  86. #define CLK_TOP_SYSPLL_D3_D8 53
  87. #define CLK_TOP_SYSPLL_D5_D2 54
  88. #define CLK_TOP_SYSPLL_D5_D4 55
  89. #define CLK_TOP_SYSPLL_D7_D2 56
  90. #define CLK_TOP_SYSPLL_D7_D4 57
  91. #define CLK_TOP_UNIVPLL_CK 58
  92. #define CLK_TOP_UNIVPLL_D2 59
  93. #define CLK_TOP_UNIVPLL_D3 60
  94. #define CLK_TOP_UNIVPLL_D5 61
  95. #define CLK_TOP_UNIVPLL_D7 62
  96. #define CLK_TOP_UNIVPLL_D2_D2 63
  97. #define CLK_TOP_UNIVPLL_D2_D4 64
  98. #define CLK_TOP_UNIVPLL_D2_D8 65
  99. #define CLK_TOP_UNIVPLL_D3_D2 66
  100. #define CLK_TOP_UNIVPLL_D3_D4 67
  101. #define CLK_TOP_UNIVPLL_D3_D8 68
  102. #define CLK_TOP_UNIVPLL_D5_D2 69
  103. #define CLK_TOP_UNIVPLL_D5_D4 70
  104. #define CLK_TOP_UNIVPLL_D5_D8 71
  105. #define CLK_TOP_APLL1_CK 72
  106. #define CLK_TOP_APLL1_D2 73
  107. #define CLK_TOP_APLL1_D4 74
  108. #define CLK_TOP_APLL1_D8 75
  109. #define CLK_TOP_APLL2_CK 76
  110. #define CLK_TOP_APLL2_D2 77
  111. #define CLK_TOP_APLL2_D4 78
  112. #define CLK_TOP_APLL2_D8 79
  113. #define CLK_TOP_TVDPLL_CK 80
  114. #define CLK_TOP_TVDPLL_D2 81
  115. #define CLK_TOP_TVDPLL_D4 82
  116. #define CLK_TOP_TVDPLL_D8 83
  117. #define CLK_TOP_TVDPLL_D16 84
  118. #define CLK_TOP_MSDCPLL_CK 85
  119. #define CLK_TOP_MSDCPLL_D2 86
  120. #define CLK_TOP_MSDCPLL_D4 87
  121. #define CLK_TOP_MSDCPLL_D8 88
  122. #define CLK_TOP_MSDCPLL_D16 89
  123. #define CLK_TOP_AD_OSC_CK 90
  124. #define CLK_TOP_OSC_D2 91
  125. #define CLK_TOP_OSC_D4 92
  126. #define CLK_TOP_OSC_D8 93
  127. #define CLK_TOP_OSC_D16 94
  128. #define CLK_TOP_F26M_CK_D2 95
  129. #define CLK_TOP_MFGPLL_CK 96
  130. #define CLK_TOP_UNIVP_192M_CK 97
  131. #define CLK_TOP_UNIVP_192M_D2 98
  132. #define CLK_TOP_UNIVP_192M_D4 99
  133. #define CLK_TOP_UNIVP_192M_D8 100
  134. #define CLK_TOP_UNIVP_192M_D16 101
  135. #define CLK_TOP_UNIVP_192M_D32 102
  136. #define CLK_TOP_MMPLL_CK 103
  137. #define CLK_TOP_MMPLL_D4 104
  138. #define CLK_TOP_MMPLL_D4_D2 105
  139. #define CLK_TOP_MMPLL_D4_D4 106
  140. #define CLK_TOP_MMPLL_D5 107
  141. #define CLK_TOP_MMPLL_D5_D2 108
  142. #define CLK_TOP_MMPLL_D5_D4 109
  143. #define CLK_TOP_MMPLL_D6 110
  144. #define CLK_TOP_MMPLL_D7 111
  145. #define CLK_TOP_CLK26M 112
  146. #define CLK_TOP_CLK13M 113
  147. #define CLK_TOP_ULPOSC 114
  148. #define CLK_TOP_UNIVP_192M 115
  149. #define CLK_TOP_MUX_APLL_I2S0 116
  150. #define CLK_TOP_MUX_APLL_I2S1 117
  151. #define CLK_TOP_MUX_APLL_I2S2 118
  152. #define CLK_TOP_MUX_APLL_I2S3 119
  153. #define CLK_TOP_MUX_APLL_I2S4 120
  154. #define CLK_TOP_MUX_APLL_I2S5 121
  155. #define CLK_TOP_APLL12_DIV0 122
  156. #define CLK_TOP_APLL12_DIV1 123
  157. #define CLK_TOP_APLL12_DIV2 124
  158. #define CLK_TOP_APLL12_DIV3 125
  159. #define CLK_TOP_APLL12_DIV4 126
  160. #define CLK_TOP_APLL12_DIVB 127
  161. #define CLK_TOP_UNIVPLL 128
  162. #define CLK_TOP_ARMPLL_DIV_PLL1 129
  163. #define CLK_TOP_ARMPLL_DIV_PLL2 130
  164. #define CLK_TOP_UNIVPLL_D3_D16 131
  165. #define CLK_TOP_NR_CLK 132
  166. /* CAMSYS */
  167. #define CLK_CAM_LARB6 0
  168. #define CLK_CAM_DFP_VAD 1
  169. #define CLK_CAM_CAM 2
  170. #define CLK_CAM_CAMTG 3
  171. #define CLK_CAM_SENINF 4
  172. #define CLK_CAM_CAMSV0 5
  173. #define CLK_CAM_CAMSV1 6
  174. #define CLK_CAM_CAMSV2 7
  175. #define CLK_CAM_CCU 8
  176. #define CLK_CAM_LARB3 9
  177. #define CLK_CAM_NR_CLK 10
  178. /* INFRACFG_AO */
  179. #define CLK_INFRA_PMIC_TMR 0
  180. #define CLK_INFRA_PMIC_AP 1
  181. #define CLK_INFRA_PMIC_MD 2
  182. #define CLK_INFRA_PMIC_CONN 3
  183. #define CLK_INFRA_SCPSYS 4
  184. #define CLK_INFRA_SEJ 5
  185. #define CLK_INFRA_APXGPT 6
  186. #define CLK_INFRA_ICUSB 7
  187. #define CLK_INFRA_GCE 8
  188. #define CLK_INFRA_THERM 9
  189. #define CLK_INFRA_I2C0 10
  190. #define CLK_INFRA_I2C1 11
  191. #define CLK_INFRA_I2C2 12
  192. #define CLK_INFRA_I2C3 13
  193. #define CLK_INFRA_PWM_HCLK 14
  194. #define CLK_INFRA_PWM1 15
  195. #define CLK_INFRA_PWM2 16
  196. #define CLK_INFRA_PWM3 17
  197. #define CLK_INFRA_PWM4 18
  198. #define CLK_INFRA_PWM 19
  199. #define CLK_INFRA_UART0 20
  200. #define CLK_INFRA_UART1 21
  201. #define CLK_INFRA_UART2 22
  202. #define CLK_INFRA_UART3 23
  203. #define CLK_INFRA_GCE_26M 24
  204. #define CLK_INFRA_CQ_DMA_FPC 25
  205. #define CLK_INFRA_BTIF 26
  206. #define CLK_INFRA_SPI0 27
  207. #define CLK_INFRA_MSDC0 28
  208. #define CLK_INFRA_MSDC1 29
  209. #define CLK_INFRA_MSDC2 30
  210. #define CLK_INFRA_MSDC0_SCK 31
  211. #define CLK_INFRA_DVFSRC 32
  212. #define CLK_INFRA_GCPU 33
  213. #define CLK_INFRA_TRNG 34
  214. #define CLK_INFRA_AUXADC 35
  215. #define CLK_INFRA_CPUM 36
  216. #define CLK_INFRA_CCIF1_AP 37
  217. #define CLK_INFRA_CCIF1_MD 38
  218. #define CLK_INFRA_AUXADC_MD 39
  219. #define CLK_INFRA_MSDC1_SCK 40
  220. #define CLK_INFRA_MSDC2_SCK 41
  221. #define CLK_INFRA_AP_DMA 42
  222. #define CLK_INFRA_XIU 43
  223. #define CLK_INFRA_DEVICE_APC 44
  224. #define CLK_INFRA_CCIF_AP 45
  225. #define CLK_INFRA_DEBUGSYS 46
  226. #define CLK_INFRA_AUDIO 47
  227. #define CLK_INFRA_CCIF_MD 48
  228. #define CLK_INFRA_DXCC_SEC_CORE 49
  229. #define CLK_INFRA_DXCC_AO 50
  230. #define CLK_INFRA_DRAMC_F26M 51
  231. #define CLK_INFRA_IRTX 52
  232. #define CLK_INFRA_DISP_PWM 53
  233. #define CLK_INFRA_CLDMA_BCLK 54
  234. #define CLK_INFRA_AUDIO_26M_BCLK 55
  235. #define CLK_INFRA_SPI1 56
  236. #define CLK_INFRA_I2C4 57
  237. #define CLK_INFRA_MODEM_TEMP_SHARE 58
  238. #define CLK_INFRA_SPI2 59
  239. #define CLK_INFRA_SPI3 60
  240. #define CLK_INFRA_UNIPRO_SCK 61
  241. #define CLK_INFRA_UNIPRO_TICK 62
  242. #define CLK_INFRA_UFS_MP_SAP_BCLK 63
  243. #define CLK_INFRA_MD32_BCLK 64
  244. #define CLK_INFRA_SSPM 65
  245. #define CLK_INFRA_UNIPRO_MBIST 66
  246. #define CLK_INFRA_SSPM_BUS_HCLK 67
  247. #define CLK_INFRA_I2C5 68
  248. #define CLK_INFRA_I2C5_ARBITER 69
  249. #define CLK_INFRA_I2C5_IMM 70
  250. #define CLK_INFRA_I2C1_ARBITER 71
  251. #define CLK_INFRA_I2C1_IMM 72
  252. #define CLK_INFRA_I2C2_ARBITER 73
  253. #define CLK_INFRA_I2C2_IMM 74
  254. #define CLK_INFRA_SPI4 75
  255. #define CLK_INFRA_SPI5 76
  256. #define CLK_INFRA_CQ_DMA 77
  257. #define CLK_INFRA_UFS 78
  258. #define CLK_INFRA_AES_UFSFDE 79
  259. #define CLK_INFRA_UFS_TICK 80
  260. #define CLK_INFRA_MSDC0_SELF 81
  261. #define CLK_INFRA_MSDC1_SELF 82
  262. #define CLK_INFRA_MSDC2_SELF 83
  263. #define CLK_INFRA_SSPM_26M_SELF 84
  264. #define CLK_INFRA_SSPM_32K_SELF 85
  265. #define CLK_INFRA_UFS_AXI 86
  266. #define CLK_INFRA_I2C6 87
  267. #define CLK_INFRA_AP_MSDC0 88
  268. #define CLK_INFRA_MD_MSDC0 89
  269. #define CLK_INFRA_USB 90
  270. #define CLK_INFRA_DEVMPU_BCLK 91
  271. #define CLK_INFRA_CCIF2_AP 92
  272. #define CLK_INFRA_CCIF2_MD 93
  273. #define CLK_INFRA_CCIF3_AP 94
  274. #define CLK_INFRA_CCIF3_MD 95
  275. #define CLK_INFRA_SEJ_F13M 96
  276. #define CLK_INFRA_AES_BCLK 97
  277. #define CLK_INFRA_I2C7 98
  278. #define CLK_INFRA_I2C8 99
  279. #define CLK_INFRA_FBIST2FPC 100
  280. #define CLK_INFRA_NR_CLK 101
  281. /* PERICFG */
  282. #define CLK_PERI_AXI 0
  283. #define CLK_PERI_NR_CLK 1
  284. /* MFGCFG */
  285. #define CLK_MFG_BG3D 0
  286. #define CLK_MFG_NR_CLK 1
  287. /* IMG */
  288. #define CLK_IMG_OWE 0
  289. #define CLK_IMG_WPE_B 1
  290. #define CLK_IMG_WPE_A 2
  291. #define CLK_IMG_MFB 3
  292. #define CLK_IMG_RSC 4
  293. #define CLK_IMG_DPE 5
  294. #define CLK_IMG_FDVT 6
  295. #define CLK_IMG_DIP 7
  296. #define CLK_IMG_LARB2 8
  297. #define CLK_IMG_LARB5 9
  298. #define CLK_IMG_NR_CLK 10
  299. /* MMSYS_CONFIG */
  300. #define CLK_MM_SMI_COMMON 0
  301. #define CLK_MM_SMI_LARB0 1
  302. #define CLK_MM_SMI_LARB1 2
  303. #define CLK_MM_GALS_COMM0 3
  304. #define CLK_MM_GALS_COMM1 4
  305. #define CLK_MM_GALS_CCU2MM 5
  306. #define CLK_MM_GALS_IPU12MM 6
  307. #define CLK_MM_GALS_IMG2MM 7
  308. #define CLK_MM_GALS_CAM2MM 8
  309. #define CLK_MM_GALS_IPU2MM 9
  310. #define CLK_MM_MDP_DL_TXCK 10
  311. #define CLK_MM_IPU_DL_TXCK 11
  312. #define CLK_MM_MDP_RDMA0 12
  313. #define CLK_MM_MDP_RDMA1 13
  314. #define CLK_MM_MDP_RSZ0 14
  315. #define CLK_MM_MDP_RSZ1 15
  316. #define CLK_MM_MDP_TDSHP 16
  317. #define CLK_MM_MDP_WROT0 17
  318. #define CLK_MM_FAKE_ENG 18
  319. #define CLK_MM_DISP_OVL0 19
  320. #define CLK_MM_DISP_OVL0_2L 20
  321. #define CLK_MM_DISP_OVL1_2L 21
  322. #define CLK_MM_DISP_RDMA0 22
  323. #define CLK_MM_DISP_RDMA1 23
  324. #define CLK_MM_DISP_WDMA0 24
  325. #define CLK_MM_DISP_COLOR0 25
  326. #define CLK_MM_DISP_CCORR0 26
  327. #define CLK_MM_DISP_AAL0 27
  328. #define CLK_MM_DISP_GAMMA0 28
  329. #define CLK_MM_DISP_DITHER0 29
  330. #define CLK_MM_DISP_SPLIT 30
  331. #define CLK_MM_DSI0_MM 31
  332. #define CLK_MM_DSI0_IF 32
  333. #define CLK_MM_DPI_MM 33
  334. #define CLK_MM_DPI_IF 34
  335. #define CLK_MM_FAKE_ENG2 35
  336. #define CLK_MM_MDP_DL_RX 36
  337. #define CLK_MM_IPU_DL_RX 37
  338. #define CLK_MM_26M 38
  339. #define CLK_MM_MMSYS_R2Y 39
  340. #define CLK_MM_DISP_RSZ 40
  341. #define CLK_MM_MDP_WDMA0 41
  342. #define CLK_MM_MDP_AAL 42
  343. #define CLK_MM_MDP_CCORR 43
  344. #define CLK_MM_DBI_MM 44
  345. #define CLK_MM_DBI_IF 45
  346. #define CLK_MM_NR_CLK 46
  347. /* VDEC_GCON */
  348. #define CLK_VDEC_VDEC 0
  349. #define CLK_VDEC_LARB1 1
  350. #define CLK_VDEC_NR_CLK 2
  351. /* VENC_GCON */
  352. #define CLK_VENC_LARB 0
  353. #define CLK_VENC_VENC 1
  354. #define CLK_VENC_JPGENC 2
  355. #define CLK_VENC_NR_CLK 3
  356. /* AUDIO */
  357. #define CLK_AUDIO_TML 0
  358. #define CLK_AUDIO_DAC_PREDIS 1
  359. #define CLK_AUDIO_DAC 2
  360. #define CLK_AUDIO_ADC 3
  361. #define CLK_AUDIO_APLL_TUNER 4
  362. #define CLK_AUDIO_APLL2_TUNER 5
  363. #define CLK_AUDIO_24M 6
  364. #define CLK_AUDIO_22M 7
  365. #define CLK_AUDIO_AFE 8
  366. #define CLK_AUDIO_I2S4 9
  367. #define CLK_AUDIO_I2S3 10
  368. #define CLK_AUDIO_I2S2 11
  369. #define CLK_AUDIO_I2S1 12
  370. #define CLK_AUDIO_PDN_ADDA6_ADC 13
  371. #define CLK_AUDIO_TDM 14
  372. #define CLK_AUDIO_NR_CLK 15
  373. /* IPU_CONN */
  374. #define CLK_IPU_CONN_IPU 0
  375. #define CLK_IPU_CONN_AHB 1
  376. #define CLK_IPU_CONN_AXI 2
  377. #define CLK_IPU_CONN_ISP 3
  378. #define CLK_IPU_CONN_CAM_ADL 4
  379. #define CLK_IPU_CONN_IMG_ADL 5
  380. #define CLK_IPU_CONN_DAP_RX 6
  381. #define CLK_IPU_CONN_APB2AXI 7
  382. #define CLK_IPU_CONN_APB2AHB 8
  383. #define CLK_IPU_CONN_IPU_CAB1TO2 9
  384. #define CLK_IPU_CONN_IPU1_CAB1TO2 10
  385. #define CLK_IPU_CONN_IPU2_CAB1TO2 11
  386. #define CLK_IPU_CONN_CAB3TO3 12
  387. #define CLK_IPU_CONN_CAB2TO1 13
  388. #define CLK_IPU_CONN_CAB3TO1_SLICE 14
  389. #define CLK_IPU_CONN_NR_CLK 15
  390. /* IPU_ADL */
  391. #define CLK_IPU_ADL_CABGEN 0
  392. #define CLK_IPU_ADL_NR_CLK 1
  393. /* IPU_CORE0 */
  394. #define CLK_IPU_CORE0_JTAG 0
  395. #define CLK_IPU_CORE0_AXI 1
  396. #define CLK_IPU_CORE0_IPU 2
  397. #define CLK_IPU_CORE0_NR_CLK 3
  398. /* IPU_CORE1 */
  399. #define CLK_IPU_CORE1_JTAG 0
  400. #define CLK_IPU_CORE1_AXI 1
  401. #define CLK_IPU_CORE1_IPU 2
  402. #define CLK_IPU_CORE1_NR_CLK 3
  403. /* MCUCFG */
  404. #define CLK_MCU_MP0_SEL 0
  405. #define CLK_MCU_MP2_SEL 1
  406. #define CLK_MCU_BUS_SEL 2
  407. #define CLK_MCU_NR_CLK 3
  408. #endif /* _DT_BINDINGS_CLK_MT8183_H */