marvell,mmp2.h 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __DTS_MARVELL_MMP2_CLOCK_H
  3. #define __DTS_MARVELL_MMP2_CLOCK_H
  4. /* fixed clocks and plls */
  5. #define MMP2_CLK_CLK32 1
  6. #define MMP2_CLK_VCTCXO 2
  7. #define MMP2_CLK_PLL1 3
  8. #define MMP2_CLK_PLL1_2 8
  9. #define MMP2_CLK_PLL1_4 9
  10. #define MMP2_CLK_PLL1_8 10
  11. #define MMP2_CLK_PLL1_16 11
  12. #define MMP2_CLK_PLL1_3 12
  13. #define MMP2_CLK_PLL1_6 13
  14. #define MMP2_CLK_PLL1_12 14
  15. #define MMP2_CLK_PLL1_20 15
  16. #define MMP2_CLK_PLL2 16
  17. #define MMP2_CLK_PLL2_2 17
  18. #define MMP2_CLK_PLL2_4 18
  19. #define MMP2_CLK_PLL2_8 19
  20. #define MMP2_CLK_PLL2_16 20
  21. #define MMP2_CLK_PLL2_3 21
  22. #define MMP2_CLK_PLL2_6 22
  23. #define MMP2_CLK_PLL2_12 23
  24. #define MMP2_CLK_VCTCXO_2 24
  25. #define MMP2_CLK_VCTCXO_4 25
  26. #define MMP2_CLK_UART_PLL 26
  27. #define MMP2_CLK_USB_PLL 27
  28. #define MMP3_CLK_PLL1_P 28
  29. #define MMP3_CLK_PLL2_P 29
  30. #define MMP3_CLK_PLL3 30
  31. #define MMP2_CLK_I2S0 31
  32. #define MMP2_CLK_I2S1 32
  33. /* apb periphrals */
  34. #define MMP2_CLK_TWSI0 60
  35. #define MMP2_CLK_TWSI1 61
  36. #define MMP2_CLK_TWSI2 62
  37. #define MMP2_CLK_TWSI3 63
  38. #define MMP2_CLK_TWSI4 64
  39. #define MMP2_CLK_TWSI5 65
  40. #define MMP2_CLK_GPIO 66
  41. #define MMP2_CLK_KPC 67
  42. #define MMP2_CLK_RTC 68
  43. #define MMP2_CLK_PWM0 69
  44. #define MMP2_CLK_PWM1 70
  45. #define MMP2_CLK_PWM2 71
  46. #define MMP2_CLK_PWM3 72
  47. #define MMP2_CLK_UART0 73
  48. #define MMP2_CLK_UART1 74
  49. #define MMP2_CLK_UART2 75
  50. #define MMP2_CLK_UART3 76
  51. #define MMP2_CLK_SSP0 77
  52. #define MMP2_CLK_SSP1 78
  53. #define MMP2_CLK_SSP2 79
  54. #define MMP2_CLK_SSP3 80
  55. #define MMP2_CLK_TIMER 81
  56. #define MMP2_CLK_THERMAL0 82
  57. #define MMP3_CLK_THERMAL1 83
  58. #define MMP3_CLK_THERMAL2 84
  59. #define MMP3_CLK_THERMAL3 85
  60. /* axi periphrals */
  61. #define MMP2_CLK_SDH0 101
  62. #define MMP2_CLK_SDH1 102
  63. #define MMP2_CLK_SDH2 103
  64. #define MMP2_CLK_SDH3 104
  65. #define MMP2_CLK_USB 105
  66. #define MMP2_CLK_DISP0 106
  67. #define MMP2_CLK_DISP0_MUX 107
  68. #define MMP2_CLK_DISP0_SPHY 108
  69. #define MMP2_CLK_DISP1 109
  70. #define MMP2_CLK_DISP1_MUX 110
  71. #define MMP2_CLK_CCIC_ARBITER 111
  72. #define MMP2_CLK_CCIC0 112
  73. #define MMP2_CLK_CCIC0_MIX 113
  74. #define MMP2_CLK_CCIC0_PHY 114
  75. #define MMP2_CLK_CCIC0_SPHY 115
  76. #define MMP2_CLK_CCIC1 116
  77. #define MMP2_CLK_CCIC1_MIX 117
  78. #define MMP2_CLK_CCIC1_PHY 118
  79. #define MMP2_CLK_CCIC1_SPHY 119
  80. #define MMP2_CLK_DISP0_LCDC 120
  81. #define MMP2_CLK_USBHSIC0 121
  82. #define MMP2_CLK_USBHSIC1 122
  83. #define MMP2_CLK_GPU_BUS 123
  84. #define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS
  85. #define MMP2_CLK_GPU_3D 124
  86. #define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D
  87. #define MMP3_CLK_GPU_2D 125
  88. #define MMP3_CLK_SDH4 126
  89. #define MMP2_CLK_AUDIO 127
  90. #define MMP2_NR_CLKS 200
  91. #endif