imx27-clock.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
  4. */
  5. #ifndef __DT_BINDINGS_CLOCK_IMX27_H
  6. #define __DT_BINDINGS_CLOCK_IMX27_H
  7. #define IMX27_CLK_DUMMY 0
  8. #define IMX27_CLK_CKIH 1
  9. #define IMX27_CLK_CKIL 2
  10. #define IMX27_CLK_MPLL 3
  11. #define IMX27_CLK_SPLL 4
  12. #define IMX27_CLK_MPLL_MAIN2 5
  13. #define IMX27_CLK_AHB 6
  14. #define IMX27_CLK_IPG 7
  15. #define IMX27_CLK_NFC_DIV 8
  16. #define IMX27_CLK_PER1_DIV 9
  17. #define IMX27_CLK_PER2_DIV 10
  18. #define IMX27_CLK_PER3_DIV 11
  19. #define IMX27_CLK_PER4_DIV 12
  20. #define IMX27_CLK_VPU_SEL 13
  21. #define IMX27_CLK_VPU_DIV 14
  22. #define IMX27_CLK_USB_DIV 15
  23. #define IMX27_CLK_CPU_SEL 16
  24. #define IMX27_CLK_CLKO_SEL 17
  25. #define IMX27_CLK_CPU_DIV 18
  26. #define IMX27_CLK_CLKO_DIV 19
  27. #define IMX27_CLK_SSI1_SEL 20
  28. #define IMX27_CLK_SSI2_SEL 21
  29. #define IMX27_CLK_SSI1_DIV 22
  30. #define IMX27_CLK_SSI2_DIV 23
  31. #define IMX27_CLK_CLKO_EN 24
  32. #define IMX27_CLK_SSI2_IPG_GATE 25
  33. #define IMX27_CLK_SSI1_IPG_GATE 26
  34. #define IMX27_CLK_SLCDC_IPG_GATE 27
  35. #define IMX27_CLK_SDHC3_IPG_GATE 28
  36. #define IMX27_CLK_SDHC2_IPG_GATE 29
  37. #define IMX27_CLK_SDHC1_IPG_GATE 30
  38. #define IMX27_CLK_SCC_IPG_GATE 31
  39. #define IMX27_CLK_SAHARA_IPG_GATE 32
  40. #define IMX27_CLK_RTC_IPG_GATE 33
  41. #define IMX27_CLK_PWM_IPG_GATE 34
  42. #define IMX27_CLK_OWIRE_IPG_GATE 35
  43. #define IMX27_CLK_LCDC_IPG_GATE 36
  44. #define IMX27_CLK_KPP_IPG_GATE 37
  45. #define IMX27_CLK_IIM_IPG_GATE 38
  46. #define IMX27_CLK_I2C2_IPG_GATE 39
  47. #define IMX27_CLK_I2C1_IPG_GATE 40
  48. #define IMX27_CLK_GPT6_IPG_GATE 41
  49. #define IMX27_CLK_GPT5_IPG_GATE 42
  50. #define IMX27_CLK_GPT4_IPG_GATE 43
  51. #define IMX27_CLK_GPT3_IPG_GATE 44
  52. #define IMX27_CLK_GPT2_IPG_GATE 45
  53. #define IMX27_CLK_GPT1_IPG_GATE 46
  54. #define IMX27_CLK_GPIO_IPG_GATE 47
  55. #define IMX27_CLK_FEC_IPG_GATE 48
  56. #define IMX27_CLK_EMMA_IPG_GATE 49
  57. #define IMX27_CLK_DMA_IPG_GATE 50
  58. #define IMX27_CLK_CSPI3_IPG_GATE 51
  59. #define IMX27_CLK_CSPI2_IPG_GATE 52
  60. #define IMX27_CLK_CSPI1_IPG_GATE 53
  61. #define IMX27_CLK_NFC_BAUD_GATE 54
  62. #define IMX27_CLK_SSI2_BAUD_GATE 55
  63. #define IMX27_CLK_SSI1_BAUD_GATE 56
  64. #define IMX27_CLK_VPU_BAUD_GATE 57
  65. #define IMX27_CLK_PER4_GATE 58
  66. #define IMX27_CLK_PER3_GATE 59
  67. #define IMX27_CLK_PER2_GATE 60
  68. #define IMX27_CLK_PER1_GATE 61
  69. #define IMX27_CLK_USB_AHB_GATE 62
  70. #define IMX27_CLK_SLCDC_AHB_GATE 63
  71. #define IMX27_CLK_SAHARA_AHB_GATE 64
  72. #define IMX27_CLK_LCDC_AHB_GATE 65
  73. #define IMX27_CLK_VPU_AHB_GATE 66
  74. #define IMX27_CLK_FEC_AHB_GATE 67
  75. #define IMX27_CLK_EMMA_AHB_GATE 68
  76. #define IMX27_CLK_EMI_AHB_GATE 69
  77. #define IMX27_CLK_DMA_AHB_GATE 70
  78. #define IMX27_CLK_CSI_AHB_GATE 71
  79. #define IMX27_CLK_BROM_AHB_GATE 72
  80. #define IMX27_CLK_ATA_AHB_GATE 73
  81. #define IMX27_CLK_WDOG_IPG_GATE 74
  82. #define IMX27_CLK_USB_IPG_GATE 75
  83. #define IMX27_CLK_UART6_IPG_GATE 76
  84. #define IMX27_CLK_UART5_IPG_GATE 77
  85. #define IMX27_CLK_UART4_IPG_GATE 78
  86. #define IMX27_CLK_UART3_IPG_GATE 79
  87. #define IMX27_CLK_UART2_IPG_GATE 80
  88. #define IMX27_CLK_UART1_IPG_GATE 81
  89. #define IMX27_CLK_CKIH_DIV1P5 82
  90. #define IMX27_CLK_FPM 83
  91. #define IMX27_CLK_MPLL_OSC_SEL 84
  92. #define IMX27_CLK_MPLL_SEL 85
  93. #define IMX27_CLK_SPLL_GATE 86
  94. #define IMX27_CLK_MSHC_DIV 87
  95. #define IMX27_CLK_RTIC_IPG_GATE 88
  96. #define IMX27_CLK_MSHC_IPG_GATE 89
  97. #define IMX27_CLK_RTIC_AHB_GATE 90
  98. #define IMX27_CLK_MSHC_BAUD_GATE 91
  99. #define IMX27_CLK_CKIH_GATE 92
  100. #define IMX27_CLK_MAX 93
  101. #endif