hix5hd2-clock.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2014 Linaro Ltd.
  4. * Copyright (c) 2014 Hisilicon Limited.
  5. */
  6. #ifndef __DTS_HIX5HD2_CLOCK_H
  7. #define __DTS_HIX5HD2_CLOCK_H
  8. /* fixed rate */
  9. #define HIX5HD2_FIXED_1200M 1
  10. #define HIX5HD2_FIXED_400M 2
  11. #define HIX5HD2_FIXED_48M 3
  12. #define HIX5HD2_FIXED_24M 4
  13. #define HIX5HD2_FIXED_600M 5
  14. #define HIX5HD2_FIXED_300M 6
  15. #define HIX5HD2_FIXED_75M 7
  16. #define HIX5HD2_FIXED_200M 8
  17. #define HIX5HD2_FIXED_100M 9
  18. #define HIX5HD2_FIXED_40M 10
  19. #define HIX5HD2_FIXED_150M 11
  20. #define HIX5HD2_FIXED_1728M 12
  21. #define HIX5HD2_FIXED_28P8M 13
  22. #define HIX5HD2_FIXED_432M 14
  23. #define HIX5HD2_FIXED_345P6M 15
  24. #define HIX5HD2_FIXED_288M 16
  25. #define HIX5HD2_FIXED_60M 17
  26. #define HIX5HD2_FIXED_750M 18
  27. #define HIX5HD2_FIXED_500M 19
  28. #define HIX5HD2_FIXED_54M 20
  29. #define HIX5HD2_FIXED_27M 21
  30. #define HIX5HD2_FIXED_1500M 22
  31. #define HIX5HD2_FIXED_375M 23
  32. #define HIX5HD2_FIXED_187M 24
  33. #define HIX5HD2_FIXED_250M 25
  34. #define HIX5HD2_FIXED_125M 26
  35. #define HIX5HD2_FIXED_2P02M 27
  36. #define HIX5HD2_FIXED_50M 28
  37. #define HIX5HD2_FIXED_25M 29
  38. #define HIX5HD2_FIXED_83M 30
  39. /* mux clocks */
  40. #define HIX5HD2_SFC_MUX 64
  41. #define HIX5HD2_MMC_MUX 65
  42. #define HIX5HD2_FEPHY_MUX 66
  43. #define HIX5HD2_SD_MUX 67
  44. /* gate clocks */
  45. #define HIX5HD2_SFC_RST 128
  46. #define HIX5HD2_SFC_CLK 129
  47. #define HIX5HD2_MMC_CIU_CLK 130
  48. #define HIX5HD2_MMC_BIU_CLK 131
  49. #define HIX5HD2_MMC_CIU_RST 132
  50. #define HIX5HD2_FWD_BUS_CLK 133
  51. #define HIX5HD2_FWD_SYS_CLK 134
  52. #define HIX5HD2_MAC0_PHY_CLK 135
  53. #define HIX5HD2_SD_CIU_CLK 136
  54. #define HIX5HD2_SD_BIU_CLK 137
  55. #define HIX5HD2_SD_CIU_RST 138
  56. #define HIX5HD2_WDG0_CLK 139
  57. #define HIX5HD2_WDG0_RST 140
  58. #define HIX5HD2_I2C0_CLK 141
  59. #define HIX5HD2_I2C0_RST 142
  60. #define HIX5HD2_I2C1_CLK 143
  61. #define HIX5HD2_I2C1_RST 144
  62. #define HIX5HD2_I2C2_CLK 145
  63. #define HIX5HD2_I2C2_RST 146
  64. #define HIX5HD2_I2C3_CLK 147
  65. #define HIX5HD2_I2C3_RST 148
  66. #define HIX5HD2_I2C4_CLK 149
  67. #define HIX5HD2_I2C4_RST 150
  68. #define HIX5HD2_I2C5_CLK 151
  69. #define HIX5HD2_I2C5_RST 152
  70. /* complex */
  71. #define HIX5HD2_MAC0_CLK 192
  72. #define HIX5HD2_MAC1_CLK 193
  73. #define HIX5HD2_SATA_CLK 194
  74. #define HIX5HD2_USB_CLK 195
  75. #define HIX5HD2_NR_CLKS 256
  76. #endif /* __DTS_HIX5HD2_CLOCK_H */