hi6220-clock.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2015 Hisilicon Limited.
  4. *
  5. * Author: Bintian Wang <bintian.wang@huawei.com>
  6. */
  7. #ifndef __DT_BINDINGS_CLOCK_HI6220_H
  8. #define __DT_BINDINGS_CLOCK_HI6220_H
  9. /* clk in Hi6220 AO (always on) controller */
  10. #define HI6220_NONE_CLOCK 0
  11. /* fixed rate clocks */
  12. #define HI6220_REF32K 1
  13. #define HI6220_CLK_TCXO 2
  14. #define HI6220_MMC1_PAD 3
  15. #define HI6220_MMC2_PAD 4
  16. #define HI6220_MMC0_PAD 5
  17. #define HI6220_PLL_BBP 6
  18. #define HI6220_PLL_GPU 7
  19. #define HI6220_PLL1_DDR 8
  20. #define HI6220_PLL_SYS 9
  21. #define HI6220_PLL_SYS_MEDIA 10
  22. #define HI6220_DDR_SRC 11
  23. #define HI6220_PLL_MEDIA 12
  24. #define HI6220_PLL_DDR 13
  25. /* fixed factor clocks */
  26. #define HI6220_300M 14
  27. #define HI6220_150M 15
  28. #define HI6220_PICOPHY_SRC 16
  29. #define HI6220_MMC0_SRC_SEL 17
  30. #define HI6220_MMC1_SRC_SEL 18
  31. #define HI6220_MMC2_SRC_SEL 19
  32. #define HI6220_VPU_CODEC 20
  33. #define HI6220_MMC0_SMP 21
  34. #define HI6220_MMC1_SMP 22
  35. #define HI6220_MMC2_SMP 23
  36. /* gate clocks */
  37. #define HI6220_WDT0_PCLK 24
  38. #define HI6220_WDT1_PCLK 25
  39. #define HI6220_WDT2_PCLK 26
  40. #define HI6220_TIMER0_PCLK 27
  41. #define HI6220_TIMER1_PCLK 28
  42. #define HI6220_TIMER2_PCLK 29
  43. #define HI6220_TIMER3_PCLK 30
  44. #define HI6220_TIMER4_PCLK 31
  45. #define HI6220_TIMER5_PCLK 32
  46. #define HI6220_TIMER6_PCLK 33
  47. #define HI6220_TIMER7_PCLK 34
  48. #define HI6220_TIMER8_PCLK 35
  49. #define HI6220_UART0_PCLK 36
  50. #define HI6220_RTC0_PCLK 37
  51. #define HI6220_RTC1_PCLK 38
  52. #define HI6220_AO_NR_CLKS 39
  53. /* clk in Hi6220 systrl */
  54. /* gate clock */
  55. #define HI6220_MMC0_CLK 1
  56. #define HI6220_MMC0_CIUCLK 2
  57. #define HI6220_MMC1_CLK 3
  58. #define HI6220_MMC1_CIUCLK 4
  59. #define HI6220_MMC2_CLK 5
  60. #define HI6220_MMC2_CIUCLK 6
  61. #define HI6220_USBOTG_HCLK 7
  62. #define HI6220_CLK_PICOPHY 8
  63. #define HI6220_HIFI 9
  64. #define HI6220_DACODEC_PCLK 10
  65. #define HI6220_EDMAC_ACLK 11
  66. #define HI6220_CS_ATB 12
  67. #define HI6220_I2C0_CLK 13
  68. #define HI6220_I2C1_CLK 14
  69. #define HI6220_I2C2_CLK 15
  70. #define HI6220_I2C3_CLK 16
  71. #define HI6220_UART1_PCLK 17
  72. #define HI6220_UART2_PCLK 18
  73. #define HI6220_UART3_PCLK 19
  74. #define HI6220_UART4_PCLK 20
  75. #define HI6220_SPI_CLK 21
  76. #define HI6220_TSENSOR_CLK 22
  77. #define HI6220_MMU_CLK 23
  78. #define HI6220_HIFI_SEL 24
  79. #define HI6220_MMC0_SYSPLL 25
  80. #define HI6220_MMC1_SYSPLL 26
  81. #define HI6220_MMC2_SYSPLL 27
  82. #define HI6220_MMC0_SEL 28
  83. #define HI6220_MMC1_SEL 29
  84. #define HI6220_BBPPLL_SEL 30
  85. #define HI6220_MEDIA_PLL_SRC 31
  86. #define HI6220_MMC2_SEL 32
  87. #define HI6220_CS_ATB_SYSPLL 33
  88. /* mux clocks */
  89. #define HI6220_MMC0_SRC 34
  90. #define HI6220_MMC0_SMP_IN 35
  91. #define HI6220_MMC1_SRC 36
  92. #define HI6220_MMC1_SMP_IN 37
  93. #define HI6220_MMC2_SRC 38
  94. #define HI6220_MMC2_SMP_IN 39
  95. #define HI6220_HIFI_SRC 40
  96. #define HI6220_UART1_SRC 41
  97. #define HI6220_UART2_SRC 42
  98. #define HI6220_UART3_SRC 43
  99. #define HI6220_UART4_SRC 44
  100. #define HI6220_MMC0_MUX0 45
  101. #define HI6220_MMC1_MUX0 46
  102. #define HI6220_MMC2_MUX0 47
  103. #define HI6220_MMC0_MUX1 48
  104. #define HI6220_MMC1_MUX1 49
  105. #define HI6220_MMC2_MUX1 50
  106. /* divider clocks */
  107. #define HI6220_CLK_BUS 51
  108. #define HI6220_MMC0_DIV 52
  109. #define HI6220_MMC1_DIV 53
  110. #define HI6220_MMC2_DIV 54
  111. #define HI6220_HIFI_DIV 55
  112. #define HI6220_BBPPLL0_DIV 56
  113. #define HI6220_CS_DAPB 57
  114. #define HI6220_CS_ATB_DIV 58
  115. /* gate clock */
  116. #define HI6220_DAPB_CLK 59
  117. #define HI6220_SYS_NR_CLKS 60
  118. /* clk in Hi6220 media controller */
  119. /* gate clocks */
  120. #define HI6220_DSI_PCLK 1
  121. #define HI6220_G3D_PCLK 2
  122. #define HI6220_ACLK_CODEC_VPU 3
  123. #define HI6220_ISP_SCLK 4
  124. #define HI6220_ADE_CORE 5
  125. #define HI6220_MED_MMU 6
  126. #define HI6220_CFG_CSI4PHY 7
  127. #define HI6220_CFG_CSI2PHY 8
  128. #define HI6220_ISP_SCLK_GATE 9
  129. #define HI6220_ISP_SCLK_GATE1 10
  130. #define HI6220_ADE_CORE_GATE 11
  131. #define HI6220_CODEC_VPU_GATE 12
  132. #define HI6220_MED_SYSPLL 13
  133. /* mux clocks */
  134. #define HI6220_1440_1200 14
  135. #define HI6220_1000_1200 15
  136. #define HI6220_1000_1440 16
  137. /* divider clocks */
  138. #define HI6220_CODEC_JPEG 17
  139. #define HI6220_ISP_SCLK_SRC 18
  140. #define HI6220_ISP_SCLK1 19
  141. #define HI6220_ADE_CORE_SRC 20
  142. #define HI6220_ADE_PIX_SRC 21
  143. #define HI6220_G3D_CLK 22
  144. #define HI6220_CODEC_VPU_SRC 23
  145. #define HI6220_MEDIA_NR_CLKS 24
  146. /* clk in Hi6220 power controller */
  147. /* gate clocks */
  148. #define HI6220_PLL_GPU_GATE 1
  149. #define HI6220_PLL1_DDR_GATE 2
  150. #define HI6220_PLL_DDR_GATE 3
  151. #define HI6220_PLL_MEDIA_GATE 4
  152. #define HI6220_PLL0_BBP_GATE 5
  153. /* divider clocks */
  154. #define HI6220_DDRC_SRC 6
  155. #define HI6220_DDRC_AXI1 7
  156. #define HI6220_POWER_NR_CLKS 8
  157. /* clk in Hi6220 acpu sctrl */
  158. #define HI6220_ACPU_SFT_AT_S 0
  159. #endif