hi3516cv300-clock.h 1.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
  4. */
  5. #ifndef __DTS_HI3516CV300_CLOCK_H
  6. #define __DTS_HI3516CV300_CLOCK_H
  7. /* hi3516CV300 core CRG */
  8. #define HI3516CV300_APB_CLK 0
  9. #define HI3516CV300_UART0_CLK 1
  10. #define HI3516CV300_UART1_CLK 2
  11. #define HI3516CV300_UART2_CLK 3
  12. #define HI3516CV300_SPI0_CLK 4
  13. #define HI3516CV300_SPI1_CLK 5
  14. #define HI3516CV300_FMC_CLK 6
  15. #define HI3516CV300_MMC0_CLK 7
  16. #define HI3516CV300_MMC1_CLK 8
  17. #define HI3516CV300_MMC2_CLK 9
  18. #define HI3516CV300_MMC3_CLK 10
  19. #define HI3516CV300_ETH_CLK 11
  20. #define HI3516CV300_ETH_MACIF_CLK 12
  21. #define HI3516CV300_DMAC_CLK 13
  22. #define HI3516CV300_PWM_CLK 14
  23. #define HI3516CV300_USB2_BUS_CLK 15
  24. #define HI3516CV300_USB2_OHCI48M_CLK 16
  25. #define HI3516CV300_USB2_OHCI12M_CLK 17
  26. #define HI3516CV300_USB2_OTG_UTMI_CLK 18
  27. #define HI3516CV300_USB2_HST_PHY_CLK 19
  28. #define HI3516CV300_USB2_UTMI0_CLK 20
  29. #define HI3516CV300_USB2_PHY_CLK 21
  30. /* hi3516CV300 sysctrl CRG */
  31. #define HI3516CV300_WDT_CLK 1
  32. #endif /* __DTS_HI3516CV300_CLOCK_H */