exynos5420.h 7.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Author: Andrzej Hajda <a.hajda@samsung.com>
  5. *
  6. * Device Tree binding constants for Exynos5420 clock controller.
  7. */
  8. #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
  9. #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
  10. /* core clocks */
  11. #define CLK_FIN_PLL 1
  12. #define CLK_FOUT_APLL 2
  13. #define CLK_FOUT_CPLL 3
  14. #define CLK_FOUT_DPLL 4
  15. #define CLK_FOUT_EPLL 5
  16. #define CLK_FOUT_RPLL 6
  17. #define CLK_FOUT_IPLL 7
  18. #define CLK_FOUT_SPLL 8
  19. #define CLK_FOUT_VPLL 9
  20. #define CLK_FOUT_MPLL 10
  21. #define CLK_FOUT_BPLL 11
  22. #define CLK_FOUT_KPLL 12
  23. #define CLK_ARM_CLK 13
  24. #define CLK_KFC_CLK 14
  25. /* gate for special clocks (sclk) */
  26. #define CLK_SCLK_UART0 128
  27. #define CLK_SCLK_UART1 129
  28. #define CLK_SCLK_UART2 130
  29. #define CLK_SCLK_UART3 131
  30. #define CLK_SCLK_MMC0 132
  31. #define CLK_SCLK_MMC1 133
  32. #define CLK_SCLK_MMC2 134
  33. #define CLK_SCLK_SPI0 135
  34. #define CLK_SCLK_SPI1 136
  35. #define CLK_SCLK_SPI2 137
  36. #define CLK_SCLK_I2S1 138
  37. #define CLK_SCLK_I2S2 139
  38. #define CLK_SCLK_PCM1 140
  39. #define CLK_SCLK_PCM2 141
  40. #define CLK_SCLK_SPDIF 142
  41. #define CLK_SCLK_HDMI 143
  42. #define CLK_SCLK_PIXEL 144
  43. #define CLK_SCLK_DP1 145
  44. #define CLK_SCLK_MIPI1 146
  45. #define CLK_SCLK_FIMD1 147
  46. #define CLK_SCLK_MAUDIO0 148
  47. #define CLK_SCLK_MAUPCM0 149
  48. #define CLK_SCLK_USBD300 150
  49. #define CLK_SCLK_USBD301 151
  50. #define CLK_SCLK_USBPHY300 152
  51. #define CLK_SCLK_USBPHY301 153
  52. #define CLK_SCLK_UNIPRO 154
  53. #define CLK_SCLK_PWM 155
  54. #define CLK_SCLK_GSCL_WA 156
  55. #define CLK_SCLK_GSCL_WB 157
  56. #define CLK_SCLK_HDMIPHY 158
  57. #define CLK_MAU_EPLL 159
  58. #define CLK_SCLK_HSIC_12M 160
  59. #define CLK_SCLK_MPHY_IXTAL24 161
  60. #define CLK_SCLK_BPLL 162
  61. /* gate clocks */
  62. #define CLK_UART0 257
  63. #define CLK_UART1 258
  64. #define CLK_UART2 259
  65. #define CLK_UART3 260
  66. #define CLK_I2C0 261
  67. #define CLK_I2C1 262
  68. #define CLK_I2C2 263
  69. #define CLK_I2C3 264
  70. #define CLK_USI0 265
  71. #define CLK_USI1 266
  72. #define CLK_USI2 267
  73. #define CLK_USI3 268
  74. #define CLK_I2C_HDMI 269
  75. #define CLK_TSADC 270
  76. #define CLK_SPI0 271
  77. #define CLK_SPI1 272
  78. #define CLK_SPI2 273
  79. #define CLK_KEYIF 274
  80. #define CLK_I2S1 275
  81. #define CLK_I2S2 276
  82. #define CLK_PCM1 277
  83. #define CLK_PCM2 278
  84. #define CLK_PWM 279
  85. #define CLK_SPDIF 280
  86. #define CLK_USI4 281
  87. #define CLK_USI5 282
  88. #define CLK_USI6 283
  89. #define CLK_ACLK66_PSGEN 300
  90. #define CLK_CHIPID 301
  91. #define CLK_SYSREG 302
  92. #define CLK_TZPC0 303
  93. #define CLK_TZPC1 304
  94. #define CLK_TZPC2 305
  95. #define CLK_TZPC3 306
  96. #define CLK_TZPC4 307
  97. #define CLK_TZPC5 308
  98. #define CLK_TZPC6 309
  99. #define CLK_TZPC7 310
  100. #define CLK_TZPC8 311
  101. #define CLK_TZPC9 312
  102. #define CLK_HDMI_CEC 313
  103. #define CLK_SECKEY 314
  104. #define CLK_MCT 315
  105. #define CLK_WDT 316
  106. #define CLK_RTC 317
  107. #define CLK_TMU 318
  108. #define CLK_TMU_GPU 319
  109. #define CLK_PCLK66_GPIO 330
  110. #define CLK_ACLK200_FSYS2 350
  111. #define CLK_MMC0 351
  112. #define CLK_MMC1 352
  113. #define CLK_MMC2 353
  114. #define CLK_SROMC 354
  115. #define CLK_UFS 355
  116. #define CLK_ACLK200_FSYS 360
  117. #define CLK_TSI 361
  118. #define CLK_PDMA0 362
  119. #define CLK_PDMA1 363
  120. #define CLK_RTIC 364
  121. #define CLK_USBH20 365
  122. #define CLK_USBD300 366
  123. #define CLK_USBD301 367
  124. #define CLK_ACLK400_MSCL 380
  125. #define CLK_MSCL0 381
  126. #define CLK_MSCL1 382
  127. #define CLK_MSCL2 383
  128. #define CLK_SMMU_MSCL0 384
  129. #define CLK_SMMU_MSCL1 385
  130. #define CLK_SMMU_MSCL2 386
  131. #define CLK_ACLK333 400
  132. #define CLK_MFC 401
  133. #define CLK_SMMU_MFCL 402
  134. #define CLK_SMMU_MFCR 403
  135. #define CLK_ACLK200_DISP1 410
  136. #define CLK_DSIM1 411
  137. #define CLK_DP1 412
  138. #define CLK_HDMI 413
  139. #define CLK_ACLK300_DISP1 420
  140. #define CLK_FIMD1 421
  141. #define CLK_SMMU_FIMD1M0 422
  142. #define CLK_SMMU_FIMD1M1 423
  143. #define CLK_ACLK166 430
  144. #define CLK_MIXER 431
  145. #define CLK_ACLK266 440
  146. #define CLK_ROTATOR 441
  147. #define CLK_MDMA1 442
  148. #define CLK_SMMU_ROTATOR 443
  149. #define CLK_SMMU_MDMA1 444
  150. #define CLK_ACLK300_JPEG 450
  151. #define CLK_JPEG 451
  152. #define CLK_JPEG2 452
  153. #define CLK_SMMU_JPEG 453
  154. #define CLK_SMMU_JPEG2 454
  155. #define CLK_ACLK300_GSCL 460
  156. #define CLK_SMMU_GSCL0 461
  157. #define CLK_SMMU_GSCL1 462
  158. #define CLK_GSCL_WA 463
  159. #define CLK_GSCL_WB 464
  160. #define CLK_GSCL0 465
  161. #define CLK_GSCL1 466
  162. #define CLK_FIMC_3AA 467
  163. #define CLK_ACLK266_G2D 470
  164. #define CLK_SSS 471
  165. #define CLK_SLIM_SSS 472
  166. #define CLK_MDMA0 473
  167. #define CLK_ACLK333_G2D 480
  168. #define CLK_G2D 481
  169. #define CLK_ACLK333_432_GSCL 490
  170. #define CLK_SMMU_3AA 491
  171. #define CLK_SMMU_FIMCL0 492
  172. #define CLK_SMMU_FIMCL1 493
  173. #define CLK_SMMU_FIMCL3 494
  174. #define CLK_FIMC_LITE3 495
  175. #define CLK_FIMC_LITE0 496
  176. #define CLK_FIMC_LITE1 497
  177. #define CLK_ACLK_G3D 500
  178. #define CLK_G3D 501
  179. #define CLK_SMMU_MIXER 502
  180. #define CLK_SMMU_G2D 503
  181. #define CLK_SMMU_MDMA0 504
  182. #define CLK_MC 505
  183. #define CLK_TOP_RTC 506
  184. #define CLK_SCLK_UART_ISP 510
  185. #define CLK_SCLK_SPI0_ISP 511
  186. #define CLK_SCLK_SPI1_ISP 512
  187. #define CLK_SCLK_PWM_ISP 513
  188. #define CLK_SCLK_ISP_SENSOR0 514
  189. #define CLK_SCLK_ISP_SENSOR1 515
  190. #define CLK_SCLK_ISP_SENSOR2 516
  191. #define CLK_ACLK432_SCALER 517
  192. #define CLK_ACLK432_CAM 518
  193. #define CLK_ACLK_FL1550_CAM 519
  194. #define CLK_ACLK550_CAM 520
  195. #define CLK_CLKM_PHY0 521
  196. #define CLK_CLKM_PHY1 522
  197. #define CLK_ACLK_PPMU_DREX0_0 523
  198. #define CLK_ACLK_PPMU_DREX0_1 524
  199. #define CLK_ACLK_PPMU_DREX1_0 525
  200. #define CLK_ACLK_PPMU_DREX1_1 526
  201. #define CLK_PCLK_PPMU_DREX0_0 527
  202. #define CLK_PCLK_PPMU_DREX0_1 528
  203. #define CLK_PCLK_PPMU_DREX1_0 529
  204. #define CLK_PCLK_PPMU_DREX1_1 530
  205. /* mux clocks */
  206. #define CLK_MOUT_HDMI 640
  207. #define CLK_MOUT_G3D 641
  208. #define CLK_MOUT_VPLL 642
  209. #define CLK_MOUT_MAUDIO0 643
  210. #define CLK_MOUT_USER_ACLK333 644
  211. #define CLK_MOUT_SW_ACLK333 645
  212. #define CLK_MOUT_USER_ACLK200_DISP1 646
  213. #define CLK_MOUT_SW_ACLK200 647
  214. #define CLK_MOUT_USER_ACLK300_DISP1 648
  215. #define CLK_MOUT_SW_ACLK300 649
  216. #define CLK_MOUT_USER_ACLK400_DISP1 650
  217. #define CLK_MOUT_SW_ACLK400 651
  218. #define CLK_MOUT_USER_ACLK300_GSCL 652
  219. #define CLK_MOUT_SW_ACLK300_GSCL 653
  220. #define CLK_MOUT_MCLK_CDREX 654
  221. #define CLK_MOUT_BPLL 655
  222. #define CLK_MOUT_MX_MSPLL_CCORE 656
  223. #define CLK_MOUT_EPLL 657
  224. #define CLK_MOUT_MAU_EPLL 658
  225. #define CLK_MOUT_USER_MAU_EPLL 659
  226. #define CLK_MOUT_SCLK_SPLL 660
  227. #define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
  228. #define CLK_MOUT_SW_ACLK_G3D 662
  229. #define CLK_MOUT_APLL 663
  230. #define CLK_MOUT_MSPLL_CPU 664
  231. #define CLK_MOUT_KPLL 665
  232. #define CLK_MOUT_MSPLL_KFC 666
  233. /* divider clocks */
  234. #define CLK_DOUT_PIXEL 768
  235. #define CLK_DOUT_ACLK400_WCORE 769
  236. #define CLK_DOUT_ACLK400_ISP 770
  237. #define CLK_DOUT_ACLK400_MSCL 771
  238. #define CLK_DOUT_ACLK200 772
  239. #define CLK_DOUT_ACLK200_FSYS2 773
  240. #define CLK_DOUT_ACLK100_NOC 774
  241. #define CLK_DOUT_PCLK200_FSYS 775
  242. #define CLK_DOUT_ACLK200_FSYS 776
  243. #define CLK_DOUT_ACLK333_432_GSCL 777
  244. #define CLK_DOUT_ACLK333_432_ISP 778
  245. #define CLK_DOUT_ACLK66 779
  246. #define CLK_DOUT_ACLK333_432_ISP0 780
  247. #define CLK_DOUT_ACLK266 781
  248. #define CLK_DOUT_ACLK166 782
  249. #define CLK_DOUT_ACLK333 783
  250. #define CLK_DOUT_ACLK333_G2D 784
  251. #define CLK_DOUT_ACLK266_G2D 785
  252. #define CLK_DOUT_ACLK_G3D 786
  253. #define CLK_DOUT_ACLK300_JPEG 787
  254. #define CLK_DOUT_ACLK300_DISP1 788
  255. #define CLK_DOUT_ACLK300_GSCL 789
  256. #define CLK_DOUT_ACLK400_DISP1 790
  257. #define CLK_DOUT_PCLK_CDREX 791
  258. #define CLK_DOUT_SCLK_CDREX 792
  259. #define CLK_DOUT_ACLK_CDREX1 793
  260. #define CLK_DOUT_CCLK_DREX0 794
  261. #define CLK_DOUT_CLK2X_PHY0 795
  262. #define CLK_DOUT_PCLK_CORE_MEM 796
  263. #define CLK_FF_DOUT_SPLL2 797
  264. #define CLK_DOUT_PCLK_DREX0 798
  265. #define CLK_DOUT_PCLK_DREX1 799
  266. /* must be greater than maximal clock id */
  267. #define CLK_NR_CLKS 800
  268. #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */