exynos5410.h 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  4. * Copyright (c) 2016 Krzysztof Kozlowski
  5. *
  6. * Device Tree binding constants for Exynos5421 clock controller.
  7. */
  8. #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
  9. #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
  10. /* core clocks */
  11. #define CLK_FIN_PLL 1
  12. #define CLK_FOUT_APLL 2
  13. #define CLK_FOUT_CPLL 3
  14. #define CLK_FOUT_MPLL 4
  15. #define CLK_FOUT_BPLL 5
  16. #define CLK_FOUT_KPLL 6
  17. #define CLK_FOUT_EPLL 7
  18. /* gate for special clocks (sclk) */
  19. #define CLK_SCLK_UART0 128
  20. #define CLK_SCLK_UART1 129
  21. #define CLK_SCLK_UART2 130
  22. #define CLK_SCLK_UART3 131
  23. #define CLK_SCLK_MMC0 132
  24. #define CLK_SCLK_MMC1 133
  25. #define CLK_SCLK_MMC2 134
  26. #define CLK_SCLK_USBD300 150
  27. #define CLK_SCLK_USBD301 151
  28. #define CLK_SCLK_USBPHY300 152
  29. #define CLK_SCLK_USBPHY301 153
  30. #define CLK_SCLK_PWM 155
  31. /* gate clocks */
  32. #define CLK_UART0 257
  33. #define CLK_UART1 258
  34. #define CLK_UART2 259
  35. #define CLK_UART3 260
  36. #define CLK_I2C0 261
  37. #define CLK_I2C1 262
  38. #define CLK_I2C2 263
  39. #define CLK_I2C3 264
  40. #define CLK_USI0 265
  41. #define CLK_USI1 266
  42. #define CLK_USI2 267
  43. #define CLK_USI3 268
  44. #define CLK_TSADC 270
  45. #define CLK_PWM 279
  46. #define CLK_MCT 315
  47. #define CLK_WDT 316
  48. #define CLK_RTC 317
  49. #define CLK_TMU 318
  50. #define CLK_MMC0 351
  51. #define CLK_MMC1 352
  52. #define CLK_MMC2 353
  53. #define CLK_PDMA0 362
  54. #define CLK_PDMA1 363
  55. #define CLK_USBH20 365
  56. #define CLK_USBD300 366
  57. #define CLK_USBD301 367
  58. #define CLK_SSS 471
  59. #define CLK_NR_CLKS 512
  60. #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */