exynos4.h 7.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Author: Andrzej Hajda <a.hajda@samsung.com>
  5. *
  6. * Device Tree binding constants for Exynos4 clock controller.
  7. */
  8. #ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
  9. #define _DT_BINDINGS_CLOCK_EXYNOS_4_H
  10. /* core clocks */
  11. #define CLK_XXTI 1
  12. #define CLK_XUSBXTI 2
  13. #define CLK_FIN_PLL 3
  14. #define CLK_FOUT_APLL 4
  15. #define CLK_FOUT_MPLL 5
  16. #define CLK_FOUT_EPLL 6
  17. #define CLK_FOUT_VPLL 7
  18. #define CLK_SCLK_APLL 8
  19. #define CLK_SCLK_MPLL 9
  20. #define CLK_SCLK_EPLL 10
  21. #define CLK_SCLK_VPLL 11
  22. #define CLK_ARM_CLK 12
  23. #define CLK_ACLK200 13
  24. #define CLK_ACLK100 14
  25. #define CLK_ACLK160 15
  26. #define CLK_ACLK133 16
  27. #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
  28. #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
  29. #define CLK_MOUT_CORE 19
  30. #define CLK_MOUT_APLL 20
  31. #define CLK_SCLK_HDMIPHY 22
  32. #define CLK_OUT_DMC 23
  33. #define CLK_OUT_TOP 24
  34. #define CLK_OUT_LEFTBUS 25
  35. #define CLK_OUT_RIGHTBUS 26
  36. #define CLK_OUT_CPU 27
  37. /* gate for special clocks (sclk) */
  38. #define CLK_SCLK_FIMC0 128
  39. #define CLK_SCLK_FIMC1 129
  40. #define CLK_SCLK_FIMC2 130
  41. #define CLK_SCLK_FIMC3 131
  42. #define CLK_SCLK_CAM0 132
  43. #define CLK_SCLK_CAM1 133
  44. #define CLK_SCLK_CSIS0 134
  45. #define CLK_SCLK_CSIS1 135
  46. #define CLK_SCLK_HDMI 136
  47. #define CLK_SCLK_MIXER 137
  48. #define CLK_SCLK_DAC 138
  49. #define CLK_SCLK_PIXEL 139
  50. #define CLK_SCLK_FIMD0 140
  51. #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
  52. #define CLK_SCLK_MDNIE_PWM0 142
  53. #define CLK_SCLK_MIPI0 143
  54. #define CLK_SCLK_AUDIO0 144
  55. #define CLK_SCLK_MMC0 145
  56. #define CLK_SCLK_MMC1 146
  57. #define CLK_SCLK_MMC2 147
  58. #define CLK_SCLK_MMC3 148
  59. #define CLK_SCLK_MMC4 149
  60. #define CLK_SCLK_SATA 150 /* Exynos4210 only */
  61. #define CLK_SCLK_UART0 151
  62. #define CLK_SCLK_UART1 152
  63. #define CLK_SCLK_UART2 153
  64. #define CLK_SCLK_UART3 154
  65. #define CLK_SCLK_UART4 155
  66. #define CLK_SCLK_AUDIO1 156
  67. #define CLK_SCLK_AUDIO2 157
  68. #define CLK_SCLK_SPDIF 158
  69. #define CLK_SCLK_SPI0 159
  70. #define CLK_SCLK_SPI1 160
  71. #define CLK_SCLK_SPI2 161
  72. #define CLK_SCLK_SLIMBUS 162
  73. #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
  74. #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
  75. #define CLK_SCLK_PCM1 165
  76. #define CLK_SCLK_PCM2 166
  77. #define CLK_SCLK_I2S1 167
  78. #define CLK_SCLK_I2S2 168
  79. #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
  80. #define CLK_SCLK_MFC 170
  81. #define CLK_SCLK_PCM0 171
  82. #define CLK_SCLK_G3D 172
  83. #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
  84. #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
  85. #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
  86. #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
  87. #define CLK_SCLK_FIMG2D 177
  88. /* gate clocks */
  89. #define CLK_SSS 255
  90. #define CLK_FIMC0 256
  91. #define CLK_FIMC1 257
  92. #define CLK_FIMC2 258
  93. #define CLK_FIMC3 259
  94. #define CLK_CSIS0 260
  95. #define CLK_CSIS1 261
  96. #define CLK_JPEG 262
  97. #define CLK_SMMU_FIMC0 263
  98. #define CLK_SMMU_FIMC1 264
  99. #define CLK_SMMU_FIMC2 265
  100. #define CLK_SMMU_FIMC3 266
  101. #define CLK_SMMU_JPEG 267
  102. #define CLK_VP 268
  103. #define CLK_MIXER 269
  104. #define CLK_TVENC 270 /* Exynos4210 only */
  105. #define CLK_HDMI 271
  106. #define CLK_SMMU_TV 272
  107. #define CLK_MFC 273
  108. #define CLK_SMMU_MFCL 274
  109. #define CLK_SMMU_MFCR 275
  110. #define CLK_G3D 276
  111. #define CLK_G2D 277
  112. #define CLK_ROTATOR 278
  113. #define CLK_MDMA 279
  114. #define CLK_SMMU_G2D 280
  115. #define CLK_SMMU_ROTATOR 281
  116. #define CLK_SMMU_MDMA 282
  117. #define CLK_FIMD0 283
  118. #define CLK_MIE0 284
  119. #define CLK_MDNIE0 285 /* Exynos4412 only */
  120. #define CLK_DSIM0 286
  121. #define CLK_SMMU_FIMD0 287
  122. #define CLK_FIMD1 288 /* Exynos4210 only */
  123. #define CLK_MIE1 289 /* Exynos4210 only */
  124. #define CLK_DSIM1 290 /* Exynos4210 only */
  125. #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
  126. #define CLK_PDMA0 292
  127. #define CLK_PDMA1 293
  128. #define CLK_PCIE_PHY 294
  129. #define CLK_SATA_PHY 295 /* Exynos4210 only */
  130. #define CLK_TSI 296
  131. #define CLK_SDMMC0 297
  132. #define CLK_SDMMC1 298
  133. #define CLK_SDMMC2 299
  134. #define CLK_SDMMC3 300
  135. #define CLK_SDMMC4 301
  136. #define CLK_SATA 302 /* Exynos4210 only */
  137. #define CLK_SROMC 303
  138. #define CLK_USB_HOST 304
  139. #define CLK_USB_DEVICE 305
  140. #define CLK_PCIE 306
  141. #define CLK_ONENAND 307
  142. #define CLK_NFCON 308
  143. #define CLK_SMMU_PCIE 309
  144. #define CLK_GPS 310
  145. #define CLK_SMMU_GPS 311
  146. #define CLK_UART0 312
  147. #define CLK_UART1 313
  148. #define CLK_UART2 314
  149. #define CLK_UART3 315
  150. #define CLK_UART4 316
  151. #define CLK_I2C0 317
  152. #define CLK_I2C1 318
  153. #define CLK_I2C2 319
  154. #define CLK_I2C3 320
  155. #define CLK_I2C4 321
  156. #define CLK_I2C5 322
  157. #define CLK_I2C6 323
  158. #define CLK_I2C7 324
  159. #define CLK_I2C_HDMI 325
  160. #define CLK_TSADC 326
  161. #define CLK_SPI0 327
  162. #define CLK_SPI1 328
  163. #define CLK_SPI2 329
  164. #define CLK_I2S1 330
  165. #define CLK_I2S2 331
  166. #define CLK_PCM0 332
  167. #define CLK_I2S0 333
  168. #define CLK_PCM1 334
  169. #define CLK_PCM2 335
  170. #define CLK_PWM 336
  171. #define CLK_SLIMBUS 337
  172. #define CLK_SPDIF 338
  173. #define CLK_AC97 339
  174. #define CLK_MODEMIF 340
  175. #define CLK_CHIPID 341
  176. #define CLK_SYSREG 342
  177. #define CLK_HDMI_CEC 343
  178. #define CLK_MCT 344
  179. #define CLK_WDT 345
  180. #define CLK_RTC 346
  181. #define CLK_KEYIF 347
  182. #define CLK_AUDSS 348
  183. #define CLK_MIPI_HSI 349 /* Exynos4210 only */
  184. #define CLK_PIXELASYNCM0 351
  185. #define CLK_PIXELASYNCM1 352
  186. #define CLK_ASYNC_G3D 353 /* Exynos4x12 only */
  187. #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
  188. #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
  189. #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
  190. #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
  191. #define CLK_TMU_APBIF 383
  192. /* mux clocks */
  193. #define CLK_MOUT_FIMC0 384
  194. #define CLK_MOUT_FIMC1 385
  195. #define CLK_MOUT_FIMC2 386
  196. #define CLK_MOUT_FIMC3 387
  197. #define CLK_MOUT_CAM0 388
  198. #define CLK_MOUT_CAM1 389
  199. #define CLK_MOUT_CSIS0 390
  200. #define CLK_MOUT_CSIS1 391
  201. #define CLK_MOUT_G3D0 392
  202. #define CLK_MOUT_G3D1 393
  203. #define CLK_MOUT_G3D 394
  204. #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
  205. #define CLK_MOUT_HDMI 396
  206. #define CLK_MOUT_MIXER 397
  207. /* gate clocks - ppmu */
  208. #define CLK_PPMULEFT 400
  209. #define CLK_PPMURIGHT 401
  210. #define CLK_PPMUCAMIF 402
  211. #define CLK_PPMUTV 403
  212. #define CLK_PPMUMFC_L 404
  213. #define CLK_PPMUMFC_R 405
  214. #define CLK_PPMUG3D 406
  215. #define CLK_PPMUIMAGE 407
  216. #define CLK_PPMULCD0 408
  217. #define CLK_PPMULCD1 409 /* Exynos4210 only */
  218. #define CLK_PPMUFILE 410
  219. #define CLK_PPMUGPS 411
  220. #define CLK_PPMUDMC0 412
  221. #define CLK_PPMUDMC1 413
  222. #define CLK_PPMUCPU 414
  223. #define CLK_PPMUACP 415
  224. /* div clocks */
  225. #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
  226. #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
  227. #define CLK_DIV_ACP 456
  228. #define CLK_DIV_DMC 457
  229. #define CLK_DIV_C2C 458 /* Exynos4x12 only */
  230. #define CLK_DIV_GDL 459
  231. #define CLK_DIV_GDR 460
  232. /* must be greater than maximal clock id */
  233. #define CLK_NR_CLKS 461
  234. /* Exynos4x12 ISP clocks */
  235. #define CLK_ISP_FIMC_ISP 1
  236. #define CLK_ISP_FIMC_DRC 2
  237. #define CLK_ISP_FIMC_FD 3
  238. #define CLK_ISP_FIMC_LITE0 4
  239. #define CLK_ISP_FIMC_LITE1 5
  240. #define CLK_ISP_MCUISP 6
  241. #define CLK_ISP_GICISP 7
  242. #define CLK_ISP_SMMU_ISP 8
  243. #define CLK_ISP_SMMU_DRC 9
  244. #define CLK_ISP_SMMU_FD 10
  245. #define CLK_ISP_SMMU_LITE0 11
  246. #define CLK_ISP_SMMU_LITE1 12
  247. #define CLK_ISP_PPMUISPMX 13
  248. #define CLK_ISP_PPMUISPX 14
  249. #define CLK_ISP_MCUCTL_ISP 15
  250. #define CLK_ISP_MPWM_ISP 16
  251. #define CLK_ISP_I2C0_ISP 17
  252. #define CLK_ISP_I2C1_ISP 18
  253. #define CLK_ISP_MTCADC_ISP 19
  254. #define CLK_ISP_PWM_ISP 20
  255. #define CLK_ISP_WDT_ISP 21
  256. #define CLK_ISP_UART_ISP 22
  257. #define CLK_ISP_ASYNCAXIM 23
  258. #define CLK_ISP_SMMU_ISPCX 24
  259. #define CLK_ISP_SPI0_ISP 25
  260. #define CLK_ISP_SPI1_ISP 26
  261. #define CLK_ISP_DIV_ISP0 27
  262. #define CLK_ISP_DIV_ISP1 28
  263. #define CLK_ISP_DIV_MCUISP0 29
  264. #define CLK_ISP_DIV_MCUISP1 30
  265. #define CLK_NR_ISP_CLKS 31
  266. #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */