i915_drm.h 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. /*
  2. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial portions
  15. * of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #ifndef _I915_DRM_H_
  27. #define _I915_DRM_H_
  28. #include <drm/i915_pciids.h>
  29. #include <uapi/drm/i915_drm.h>
  30. /* For use by IPS driver */
  31. unsigned long i915_read_mch_val(void);
  32. bool i915_gpu_raise(void);
  33. bool i915_gpu_lower(void);
  34. bool i915_gpu_busy(void);
  35. bool i915_gpu_turbo_disable(void);
  36. /* Exported from arch/x86/kernel/early-quirks.c */
  37. extern struct resource intel_graphics_stolen_res;
  38. /*
  39. * The Bridge device's PCI config space has information about the
  40. * fb aperture size and the amount of pre-reserved memory.
  41. * This is all handled in the intel-gtt.ko module. i915.ko only
  42. * cares about the vga bit for the vga rbiter.
  43. */
  44. #define INTEL_GMCH_CTRL 0x52
  45. #define INTEL_GMCH_VGA_DISABLE (1 << 1)
  46. #define SNB_GMCH_CTRL 0x50
  47. #define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
  48. #define SNB_GMCH_GGMS_MASK 0x3
  49. #define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
  50. #define SNB_GMCH_GMS_MASK 0x1f
  51. #define BDW_GMCH_GGMS_SHIFT 6
  52. #define BDW_GMCH_GGMS_MASK 0x3
  53. #define BDW_GMCH_GMS_SHIFT 8
  54. #define BDW_GMCH_GMS_MASK 0xff
  55. #define I830_GMCH_CTRL 0x52
  56. #define I830_GMCH_GMS_MASK 0x70
  57. #define I830_GMCH_GMS_LOCAL 0x10
  58. #define I830_GMCH_GMS_STOLEN_512 0x20
  59. #define I830_GMCH_GMS_STOLEN_1024 0x30
  60. #define I830_GMCH_GMS_STOLEN_8192 0x40
  61. #define I855_GMCH_GMS_MASK 0xF0
  62. #define I855_GMCH_GMS_STOLEN_0M 0x0
  63. #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
  64. #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
  65. #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
  66. #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
  67. #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
  68. #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
  69. #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
  70. #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
  71. #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
  72. #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
  73. #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
  74. #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
  75. #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
  76. #define I830_DRB3 0x63
  77. #define I85X_DRB3 0x43
  78. #define I865_TOUD 0xc4
  79. #define I830_ESMRAMC 0x91
  80. #define I845_ESMRAMC 0x9e
  81. #define I85X_ESMRAMC 0x61
  82. #define TSEG_ENABLE (1 << 0)
  83. #define I830_TSEG_SIZE_512K (0 << 1)
  84. #define I830_TSEG_SIZE_1M (1 << 1)
  85. #define I845_TSEG_SIZE_MASK (3 << 1)
  86. #define I845_TSEG_SIZE_512K (2 << 1)
  87. #define I845_TSEG_SIZE_1M (3 << 1)
  88. #define INTEL_BSM 0x5c
  89. #define INTEL_GEN11_BSM_DW0 0xc0
  90. #define INTEL_GEN11_BSM_DW1 0xc4
  91. #define INTEL_BSM_MASK (-(1u << 20))
  92. #endif /* _I915_DRM_H_ */