drm_scdc_helper.h 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136
  1. /*
  2. * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sub license,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the
  12. * next paragraph) shall be included in all copies or substantial portions
  13. * of the Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. */
  23. #ifndef DRM_SCDC_HELPER_H
  24. #define DRM_SCDC_HELPER_H
  25. #include <linux/i2c.h>
  26. #include <linux/types.h>
  27. #define SCDC_SINK_VERSION 0x01
  28. #define SCDC_SOURCE_VERSION 0x02
  29. #define SCDC_UPDATE_0 0x10
  30. #define SCDC_READ_REQUEST_TEST (1 << 2)
  31. #define SCDC_CED_UPDATE (1 << 1)
  32. #define SCDC_STATUS_UPDATE (1 << 0)
  33. #define SCDC_UPDATE_1 0x11
  34. #define SCDC_TMDS_CONFIG 0x20
  35. #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
  36. #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
  37. #define SCDC_SCRAMBLING_ENABLE (1 << 0)
  38. #define SCDC_SCRAMBLER_STATUS 0x21
  39. #define SCDC_SCRAMBLING_STATUS (1 << 0)
  40. #define SCDC_CONFIG_0 0x30
  41. #define SCDC_READ_REQUEST_ENABLE (1 << 0)
  42. #define SCDC_STATUS_FLAGS_0 0x40
  43. #define SCDC_CH2_LOCK (1 << 3)
  44. #define SCDC_CH1_LOCK (1 << 2)
  45. #define SCDC_CH0_LOCK (1 << 1)
  46. #define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
  47. #define SCDC_CLOCK_DETECT (1 << 0)
  48. #define SCDC_STATUS_FLAGS_1 0x41
  49. #define SCDC_ERR_DET_0_L 0x50
  50. #define SCDC_ERR_DET_0_H 0x51
  51. #define SCDC_ERR_DET_1_L 0x52
  52. #define SCDC_ERR_DET_1_H 0x53
  53. #define SCDC_ERR_DET_2_L 0x54
  54. #define SCDC_ERR_DET_2_H 0x55
  55. #define SCDC_CHANNEL_VALID (1 << 7)
  56. #define SCDC_ERR_DET_CHECKSUM 0x56
  57. #define SCDC_TEST_CONFIG_0 0xc0
  58. #define SCDC_TEST_READ_REQUEST (1 << 7)
  59. #define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
  60. #define SCDC_MANUFACTURER_IEEE_OUI 0xd0
  61. #define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
  62. #define SCDC_DEVICE_ID 0xd3
  63. #define SCDC_DEVICE_ID_SIZE 8
  64. #define SCDC_DEVICE_HARDWARE_REVISION 0xdb
  65. #define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
  66. #define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
  67. #define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
  68. #define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
  69. #define SCDC_MANUFACTURER_SPECIFIC 0xde
  70. #define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
  71. ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
  72. size_t size);
  73. ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
  74. const void *buffer, size_t size);
  75. /**
  76. * drm_scdc_readb - read a single byte from SCDC
  77. * @adapter: I2C adapter
  78. * @offset: offset of register to read
  79. * @value: return location for the register value
  80. *
  81. * Reads a single byte from SCDC. This is a convenience wrapper around the
  82. * drm_scdc_read() function.
  83. *
  84. * Returns:
  85. * 0 on success or a negative error code on failure.
  86. */
  87. static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset,
  88. u8 *value)
  89. {
  90. return drm_scdc_read(adapter, offset, value, sizeof(*value));
  91. }
  92. /**
  93. * drm_scdc_writeb - write a single byte to SCDC
  94. * @adapter: I2C adapter
  95. * @offset: offset of register to read
  96. * @value: return location for the register value
  97. *
  98. * Writes a single byte to SCDC. This is a convenience wrapper around the
  99. * drm_scdc_write() function.
  100. *
  101. * Returns:
  102. * 0 on success or a negative error code on failure.
  103. */
  104. static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
  105. u8 value)
  106. {
  107. return drm_scdc_write(adapter, offset, &value, sizeof(value));
  108. }
  109. bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter);
  110. bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
  111. bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
  112. #endif