drm_dp_helper.h 70 KB

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  1. /*
  2. * Copyright © 2008 Keith Packard
  3. *
  4. * Permission to use, copy, modify, distribute, and sell this software and its
  5. * documentation for any purpose is hereby granted without fee, provided that
  6. * the above copyright notice appear in all copies and that both that copyright
  7. * notice and this permission notice appear in supporting documentation, and
  8. * that the name of the copyright holders not be used in advertising or
  9. * publicity pertaining to distribution of the software without specific,
  10. * written prior permission. The copyright holders make no representations
  11. * about the suitability of this software for any purpose. It is provided "as
  12. * is" without express or implied warranty.
  13. *
  14. * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15. * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16. * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18. * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20. * OF THIS SOFTWARE.
  21. */
  22. #ifndef _DRM_DP_HELPER_H_
  23. #define _DRM_DP_HELPER_H_
  24. #include <linux/delay.h>
  25. #include <linux/i2c.h>
  26. #include <linux/types.h>
  27. #include <drm/drm_connector.h>
  28. struct drm_device;
  29. /*
  30. * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
  31. * DP and DPCD versions are independent. Differences from 1.0 are not noted,
  32. * 1.0 devices basically don't exist in the wild.
  33. *
  34. * Abbreviations, in chronological order:
  35. *
  36. * eDP: Embedded DisplayPort version 1
  37. * DPI: DisplayPort Interoperability Guideline v1.1a
  38. * 1.2: DisplayPort 1.2
  39. * MST: Multistream Transport - part of DP 1.2a
  40. *
  41. * 1.2 formally includes both eDP and DPI definitions.
  42. */
  43. /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
  44. #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
  45. #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
  46. #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
  47. #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
  48. #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
  49. /* bits per component for non-RAW */
  50. #define DP_MSA_MISC_6_BPC (0 << 5)
  51. #define DP_MSA_MISC_8_BPC (1 << 5)
  52. #define DP_MSA_MISC_10_BPC (2 << 5)
  53. #define DP_MSA_MISC_12_BPC (3 << 5)
  54. #define DP_MSA_MISC_16_BPC (4 << 5)
  55. /* bits per component for RAW */
  56. #define DP_MSA_MISC_RAW_6_BPC (1 << 5)
  57. #define DP_MSA_MISC_RAW_7_BPC (2 << 5)
  58. #define DP_MSA_MISC_RAW_8_BPC (3 << 5)
  59. #define DP_MSA_MISC_RAW_10_BPC (4 << 5)
  60. #define DP_MSA_MISC_RAW_12_BPC (5 << 5)
  61. #define DP_MSA_MISC_RAW_14_BPC (6 << 5)
  62. #define DP_MSA_MISC_RAW_16_BPC (7 << 5)
  63. /* pixel encoding/colorimetry format */
  64. #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
  65. ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
  66. #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
  67. #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
  68. #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
  69. #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
  70. #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
  71. #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
  72. #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
  73. #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
  74. #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
  75. #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
  76. #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
  77. #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
  78. #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
  79. #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
  80. #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
  81. #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
  82. #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
  83. #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
  84. #define DP_AUX_MAX_PAYLOAD_BYTES 16
  85. #define DP_AUX_I2C_WRITE 0x0
  86. #define DP_AUX_I2C_READ 0x1
  87. #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
  88. #define DP_AUX_I2C_MOT 0x4
  89. #define DP_AUX_NATIVE_WRITE 0x8
  90. #define DP_AUX_NATIVE_READ 0x9
  91. #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
  92. #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
  93. #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
  94. #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
  95. #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
  96. #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
  97. #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
  98. #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
  99. /* AUX CH addresses */
  100. /* DPCD */
  101. #define DP_DPCD_REV 0x000
  102. # define DP_DPCD_REV_10 0x10
  103. # define DP_DPCD_REV_11 0x11
  104. # define DP_DPCD_REV_12 0x12
  105. # define DP_DPCD_REV_13 0x13
  106. # define DP_DPCD_REV_14 0x14
  107. #define DP_MAX_LINK_RATE 0x001
  108. #define DP_MAX_LANE_COUNT 0x002
  109. # define DP_MAX_LANE_COUNT_MASK 0x1f
  110. # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
  111. # define DP_ENHANCED_FRAME_CAP (1 << 7)
  112. #define DP_MAX_DOWNSPREAD 0x003
  113. # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
  114. # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
  115. # define DP_TPS4_SUPPORTED (1 << 7)
  116. #define DP_NORP 0x004
  117. #define DP_DOWNSTREAMPORT_PRESENT 0x005
  118. # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
  119. # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
  120. # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
  121. # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
  122. # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
  123. # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
  124. # define DP_FORMAT_CONVERSION (1 << 3)
  125. # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
  126. #define DP_MAIN_LINK_CHANNEL_CODING 0x006
  127. # define DP_CAP_ANSI_8B10B (1 << 0)
  128. #define DP_DOWN_STREAM_PORT_COUNT 0x007
  129. # define DP_PORT_COUNT_MASK 0x0f
  130. # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
  131. # define DP_OUI_SUPPORT (1 << 7)
  132. #define DP_RECEIVE_PORT_0_CAP_0 0x008
  133. # define DP_LOCAL_EDID_PRESENT (1 << 1)
  134. # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
  135. #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
  136. #define DP_RECEIVE_PORT_1_CAP_0 0x00a
  137. #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
  138. #define DP_I2C_SPEED_CAP 0x00c /* DPI */
  139. # define DP_I2C_SPEED_1K 0x01
  140. # define DP_I2C_SPEED_5K 0x02
  141. # define DP_I2C_SPEED_10K 0x04
  142. # define DP_I2C_SPEED_100K 0x08
  143. # define DP_I2C_SPEED_400K 0x10
  144. # define DP_I2C_SPEED_1M 0x20
  145. #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
  146. # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
  147. # define DP_FRAMING_CHANGE_CAP (1 << 1)
  148. # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
  149. #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
  150. # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
  151. # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
  152. #define DP_ADAPTER_CAP 0x00f /* 1.2 */
  153. # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
  154. # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
  155. #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
  156. # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
  157. /* Multiple stream transport */
  158. #define DP_FAUX_CAP 0x020 /* 1.2 */
  159. # define DP_FAUX_CAP_1 (1 << 0)
  160. #define DP_MSTM_CAP 0x021 /* 1.2 */
  161. # define DP_MST_CAP (1 << 0)
  162. #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
  163. /* AV_SYNC_DATA_BLOCK 1.2 */
  164. #define DP_AV_GRANULARITY 0x023
  165. # define DP_AG_FACTOR_MASK (0xf << 0)
  166. # define DP_AG_FACTOR_3MS (0 << 0)
  167. # define DP_AG_FACTOR_2MS (1 << 0)
  168. # define DP_AG_FACTOR_1MS (2 << 0)
  169. # define DP_AG_FACTOR_500US (3 << 0)
  170. # define DP_AG_FACTOR_200US (4 << 0)
  171. # define DP_AG_FACTOR_100US (5 << 0)
  172. # define DP_AG_FACTOR_10US (6 << 0)
  173. # define DP_AG_FACTOR_1US (7 << 0)
  174. # define DP_VG_FACTOR_MASK (0xf << 4)
  175. # define DP_VG_FACTOR_3MS (0 << 4)
  176. # define DP_VG_FACTOR_2MS (1 << 4)
  177. # define DP_VG_FACTOR_1MS (2 << 4)
  178. # define DP_VG_FACTOR_500US (3 << 4)
  179. # define DP_VG_FACTOR_200US (4 << 4)
  180. # define DP_VG_FACTOR_100US (5 << 4)
  181. #define DP_AUD_DEC_LAT0 0x024
  182. #define DP_AUD_DEC_LAT1 0x025
  183. #define DP_AUD_PP_LAT0 0x026
  184. #define DP_AUD_PP_LAT1 0x027
  185. #define DP_VID_INTER_LAT 0x028
  186. #define DP_VID_PROG_LAT 0x029
  187. #define DP_REP_LAT 0x02a
  188. #define DP_AUD_DEL_INS0 0x02b
  189. #define DP_AUD_DEL_INS1 0x02c
  190. #define DP_AUD_DEL_INS2 0x02d
  191. /* End of AV_SYNC_DATA_BLOCK */
  192. #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
  193. # define DP_ALPM_CAP (1 << 0)
  194. #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
  195. # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
  196. #define DP_GUID 0x030 /* 1.2 */
  197. #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
  198. # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
  199. #define DP_DSC_REV 0x061
  200. # define DP_DSC_MAJOR_MASK (0xf << 0)
  201. # define DP_DSC_MINOR_MASK (0xf << 4)
  202. # define DP_DSC_MAJOR_SHIFT 0
  203. # define DP_DSC_MINOR_SHIFT 4
  204. #define DP_DSC_RC_BUF_BLK_SIZE 0x062
  205. # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
  206. # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
  207. # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
  208. # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
  209. #define DP_DSC_RC_BUF_SIZE 0x063
  210. #define DP_DSC_SLICE_CAP_1 0x064
  211. # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
  212. # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
  213. # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
  214. # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
  215. # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
  216. # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
  217. # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
  218. #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
  219. # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
  220. # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
  221. # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
  222. # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
  223. # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
  224. # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
  225. # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
  226. # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
  227. # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
  228. # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
  229. #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
  230. # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
  231. #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
  232. #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
  233. # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
  234. # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
  235. #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
  236. # define DP_DSC_RGB (1 << 0)
  237. # define DP_DSC_YCbCr444 (1 << 1)
  238. # define DP_DSC_YCbCr422_Simple (1 << 2)
  239. # define DP_DSC_YCbCr422_Native (1 << 3)
  240. # define DP_DSC_YCbCr420_Native (1 << 4)
  241. #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
  242. # define DP_DSC_8_BPC (1 << 1)
  243. # define DP_DSC_10_BPC (1 << 2)
  244. # define DP_DSC_12_BPC (1 << 3)
  245. #define DP_DSC_PEAK_THROUGHPUT 0x06B
  246. # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
  247. # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
  248. # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
  249. # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
  250. # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
  251. # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
  252. # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
  253. # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
  254. # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
  255. # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
  256. # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
  257. # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
  258. # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
  259. # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
  260. # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
  261. # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
  262. # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
  263. # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
  264. # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
  265. # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
  266. # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
  267. # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
  268. # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
  269. # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
  270. # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
  271. # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
  272. # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
  273. # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
  274. # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
  275. # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
  276. # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
  277. # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
  278. # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
  279. # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
  280. # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
  281. # define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
  282. #define DP_DSC_MAX_SLICE_WIDTH 0x06C
  283. #define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
  284. #define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
  285. #define DP_DSC_SLICE_CAP_2 0x06D
  286. # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
  287. # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
  288. # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
  289. #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
  290. # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
  291. # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
  292. # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
  293. # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
  294. # define DP_DSC_BITS_PER_PIXEL_1 0x4
  295. #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
  296. # define DP_PSR_IS_SUPPORTED 1
  297. # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
  298. # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
  299. #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
  300. # define DP_PSR_NO_TRAIN_ON_EXIT 1
  301. # define DP_PSR_SETUP_TIME_330 (0 << 1)
  302. # define DP_PSR_SETUP_TIME_275 (1 << 1)
  303. # define DP_PSR_SETUP_TIME_220 (2 << 1)
  304. # define DP_PSR_SETUP_TIME_165 (3 << 1)
  305. # define DP_PSR_SETUP_TIME_110 (4 << 1)
  306. # define DP_PSR_SETUP_TIME_55 (5 << 1)
  307. # define DP_PSR_SETUP_TIME_0 (6 << 1)
  308. # define DP_PSR_SETUP_TIME_MASK (7 << 1)
  309. # define DP_PSR_SETUP_TIME_SHIFT 1
  310. # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
  311. # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
  312. #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
  313. #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
  314. /*
  315. * 0x80-0x8f describe downstream port capabilities, but there are two layouts
  316. * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
  317. * each port's descriptor is one byte wide. If it was set, each port's is
  318. * four bytes wide, starting with the one byte from the base info. As of
  319. * DP interop v1.1a only VGA defines additional detail.
  320. */
  321. /* offset 0 */
  322. #define DP_DOWNSTREAM_PORT_0 0x80
  323. # define DP_DS_PORT_TYPE_MASK (7 << 0)
  324. # define DP_DS_PORT_TYPE_DP 0
  325. # define DP_DS_PORT_TYPE_VGA 1
  326. # define DP_DS_PORT_TYPE_DVI 2
  327. # define DP_DS_PORT_TYPE_HDMI 3
  328. # define DP_DS_PORT_TYPE_NON_EDID 4
  329. # define DP_DS_PORT_TYPE_DP_DUALMODE 5
  330. # define DP_DS_PORT_TYPE_WIRELESS 6
  331. # define DP_DS_PORT_HPD (1 << 3)
  332. # define DP_DS_NON_EDID_MASK (0xf << 4)
  333. # define DP_DS_NON_EDID_720x480i_60 (1 << 4)
  334. # define DP_DS_NON_EDID_720x480i_50 (2 << 4)
  335. # define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
  336. # define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
  337. # define DP_DS_NON_EDID_1280x720_60 (5 << 4)
  338. # define DP_DS_NON_EDID_1280x720_50 (7 << 4)
  339. /* offset 1 for VGA is maximum megapixels per second / 8 */
  340. /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
  341. /* offset 2 for VGA/DVI/HDMI */
  342. # define DP_DS_MAX_BPC_MASK (3 << 0)
  343. # define DP_DS_8BPC 0
  344. # define DP_DS_10BPC 1
  345. # define DP_DS_12BPC 2
  346. # define DP_DS_16BPC 3
  347. /* offset 3 for DVI */
  348. # define DP_DS_DVI_DUAL_LINK (1 << 1)
  349. # define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)
  350. /* offset 3 for HDMI */
  351. # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
  352. # define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
  353. # define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
  354. # define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)
  355. # define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)
  356. #define DP_MAX_DOWNSTREAM_PORTS 0x10
  357. /* DP Forward error Correction Registers */
  358. #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
  359. # define DP_FEC_CAPABLE (1 << 0)
  360. # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
  361. # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
  362. # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
  363. /* DP Extended DSC Capabilities */
  364. #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
  365. #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
  366. #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
  367. /* link configuration */
  368. #define DP_LINK_BW_SET 0x100
  369. # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
  370. # define DP_LINK_BW_1_62 0x06
  371. # define DP_LINK_BW_2_7 0x0a
  372. # define DP_LINK_BW_5_4 0x14 /* 1.2 */
  373. # define DP_LINK_BW_8_1 0x1e /* 1.4 */
  374. #define DP_LANE_COUNT_SET 0x101
  375. # define DP_LANE_COUNT_MASK 0x0f
  376. # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
  377. #define DP_TRAINING_PATTERN_SET 0x102
  378. # define DP_TRAINING_PATTERN_DISABLE 0
  379. # define DP_TRAINING_PATTERN_1 1
  380. # define DP_TRAINING_PATTERN_2 2
  381. # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
  382. # define DP_TRAINING_PATTERN_4 7 /* 1.4 */
  383. # define DP_TRAINING_PATTERN_MASK 0x3
  384. # define DP_TRAINING_PATTERN_MASK_1_4 0xf
  385. /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
  386. # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
  387. # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
  388. # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
  389. # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
  390. # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
  391. # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
  392. # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
  393. # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
  394. # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
  395. # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
  396. # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
  397. #define DP_TRAINING_LANE0_SET 0x103
  398. #define DP_TRAINING_LANE1_SET 0x104
  399. #define DP_TRAINING_LANE2_SET 0x105
  400. #define DP_TRAINING_LANE3_SET 0x106
  401. # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
  402. # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
  403. # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
  404. # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
  405. # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
  406. # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
  407. # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
  408. # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
  409. # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
  410. # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
  411. # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
  412. # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
  413. # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
  414. # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
  415. #define DP_DOWNSPREAD_CTRL 0x107
  416. # define DP_SPREAD_AMP_0_5 (1 << 4)
  417. # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
  418. #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
  419. # define DP_SET_ANSI_8B10B (1 << 0)
  420. #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
  421. /* bitmask as for DP_I2C_SPEED_CAP */
  422. #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
  423. # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
  424. # define DP_FRAMING_CHANGE_ENABLE (1 << 1)
  425. # define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
  426. #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
  427. #define DP_LINK_QUAL_LANE1_SET 0x10c
  428. #define DP_LINK_QUAL_LANE2_SET 0x10d
  429. #define DP_LINK_QUAL_LANE3_SET 0x10e
  430. # define DP_LINK_QUAL_PATTERN_DISABLE 0
  431. # define DP_LINK_QUAL_PATTERN_D10_2 1
  432. # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
  433. # define DP_LINK_QUAL_PATTERN_PRBS7 3
  434. # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
  435. # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
  436. # define DP_LINK_QUAL_PATTERN_MASK 7
  437. #define DP_TRAINING_LANE0_1_SET2 0x10f
  438. #define DP_TRAINING_LANE2_3_SET2 0x110
  439. # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
  440. # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
  441. # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
  442. # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
  443. #define DP_MSTM_CTRL 0x111 /* 1.2 */
  444. # define DP_MST_EN (1 << 0)
  445. # define DP_UP_REQ_EN (1 << 1)
  446. # define DP_UPSTREAM_IS_SRC (1 << 2)
  447. #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
  448. #define DP_AUDIO_DELAY1 0x113
  449. #define DP_AUDIO_DELAY2 0x114
  450. #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
  451. # define DP_LINK_RATE_SET_SHIFT 0
  452. # define DP_LINK_RATE_SET_MASK (7 << 0)
  453. #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
  454. # define DP_ALPM_ENABLE (1 << 0)
  455. # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
  456. #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
  457. # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
  458. # define DP_IRQ_HPD_ENABLE (1 << 1)
  459. #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
  460. # define DP_PWR_NOT_NEEDED (1 << 0)
  461. #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
  462. # define DP_FEC_READY (1 << 0)
  463. # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
  464. # define DP_FEC_ERR_COUNT_DIS (0 << 1)
  465. # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
  466. # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
  467. # define DP_FEC_BIT_ERROR_COUNT (3 << 1)
  468. # define DP_FEC_LANE_SELECT_MASK (3 << 4)
  469. # define DP_FEC_LANE_0_SELECT (0 << 4)
  470. # define DP_FEC_LANE_1_SELECT (1 << 4)
  471. # define DP_FEC_LANE_2_SELECT (2 << 4)
  472. # define DP_FEC_LANE_3_SELECT (3 << 4)
  473. #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
  474. # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
  475. #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
  476. # define DP_DECOMPRESSION_EN (1 << 0)
  477. #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
  478. # define DP_PSR_ENABLE (1 << 0)
  479. # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
  480. # define DP_PSR_CRC_VERIFICATION (1 << 2)
  481. # define DP_PSR_FRAME_CAPTURE (1 << 3)
  482. # define DP_PSR_SELECTIVE_UPDATE (1 << 4)
  483. # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
  484. # define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */
  485. #define DP_ADAPTER_CTRL 0x1a0
  486. # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
  487. #define DP_BRANCH_DEVICE_CTRL 0x1a1
  488. # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
  489. #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
  490. #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
  491. #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
  492. #define DP_SINK_COUNT 0x200
  493. /* prior to 1.2 bit 7 was reserved mbz */
  494. # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
  495. # define DP_SINK_CP_READY (1 << 6)
  496. #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
  497. # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
  498. # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
  499. # define DP_CP_IRQ (1 << 2)
  500. # define DP_MCCS_IRQ (1 << 3)
  501. # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
  502. # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
  503. # define DP_SINK_SPECIFIC_IRQ (1 << 6)
  504. #define DP_LANE0_1_STATUS 0x202
  505. #define DP_LANE2_3_STATUS 0x203
  506. # define DP_LANE_CR_DONE (1 << 0)
  507. # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
  508. # define DP_LANE_SYMBOL_LOCKED (1 << 2)
  509. #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
  510. DP_LANE_CHANNEL_EQ_DONE | \
  511. DP_LANE_SYMBOL_LOCKED)
  512. #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
  513. #define DP_INTERLANE_ALIGN_DONE (1 << 0)
  514. #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
  515. #define DP_LINK_STATUS_UPDATED (1 << 7)
  516. #define DP_SINK_STATUS 0x205
  517. #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
  518. #define DP_RECEIVE_PORT_1_STATUS (1 << 1)
  519. #define DP_ADJUST_REQUEST_LANE0_1 0x206
  520. #define DP_ADJUST_REQUEST_LANE2_3 0x207
  521. # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
  522. # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
  523. # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
  524. # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
  525. # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
  526. # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
  527. # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
  528. # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
  529. #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
  530. # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
  531. # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
  532. # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
  533. # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
  534. # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
  535. # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
  536. # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
  537. # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
  538. #define DP_TEST_REQUEST 0x218
  539. # define DP_TEST_LINK_TRAINING (1 << 0)
  540. # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
  541. # define DP_TEST_LINK_EDID_READ (1 << 2)
  542. # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
  543. # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
  544. # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
  545. # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
  546. #define DP_TEST_LINK_RATE 0x219
  547. # define DP_LINK_RATE_162 (0x6)
  548. # define DP_LINK_RATE_27 (0xa)
  549. #define DP_TEST_LANE_COUNT 0x220
  550. #define DP_TEST_PATTERN 0x221
  551. # define DP_NO_TEST_PATTERN 0x0
  552. # define DP_COLOR_RAMP 0x1
  553. # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
  554. # define DP_COLOR_SQUARE 0x3
  555. #define DP_TEST_H_TOTAL_HI 0x222
  556. #define DP_TEST_H_TOTAL_LO 0x223
  557. #define DP_TEST_V_TOTAL_HI 0x224
  558. #define DP_TEST_V_TOTAL_LO 0x225
  559. #define DP_TEST_H_START_HI 0x226
  560. #define DP_TEST_H_START_LO 0x227
  561. #define DP_TEST_V_START_HI 0x228
  562. #define DP_TEST_V_START_LO 0x229
  563. #define DP_TEST_HSYNC_HI 0x22A
  564. # define DP_TEST_HSYNC_POLARITY (1 << 7)
  565. # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
  566. #define DP_TEST_HSYNC_WIDTH_LO 0x22B
  567. #define DP_TEST_VSYNC_HI 0x22C
  568. # define DP_TEST_VSYNC_POLARITY (1 << 7)
  569. # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
  570. #define DP_TEST_VSYNC_WIDTH_LO 0x22D
  571. #define DP_TEST_H_WIDTH_HI 0x22E
  572. #define DP_TEST_H_WIDTH_LO 0x22F
  573. #define DP_TEST_V_HEIGHT_HI 0x230
  574. #define DP_TEST_V_HEIGHT_LO 0x231
  575. #define DP_TEST_MISC0 0x232
  576. # define DP_TEST_SYNC_CLOCK (1 << 0)
  577. # define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
  578. # define DP_TEST_COLOR_FORMAT_SHIFT 1
  579. # define DP_COLOR_FORMAT_RGB (0 << 1)
  580. # define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
  581. # define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
  582. # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
  583. # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
  584. # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
  585. # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
  586. # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
  587. # define DP_TEST_BIT_DEPTH_MASK (7 << 5)
  588. # define DP_TEST_BIT_DEPTH_SHIFT 5
  589. # define DP_TEST_BIT_DEPTH_6 (0 << 5)
  590. # define DP_TEST_BIT_DEPTH_8 (1 << 5)
  591. # define DP_TEST_BIT_DEPTH_10 (2 << 5)
  592. # define DP_TEST_BIT_DEPTH_12 (3 << 5)
  593. # define DP_TEST_BIT_DEPTH_16 (4 << 5)
  594. #define DP_TEST_MISC1 0x233
  595. # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
  596. # define DP_TEST_INTERLACED (1 << 1)
  597. #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
  598. #define DP_TEST_MISC0 0x232
  599. #define DP_TEST_CRC_R_CR 0x240
  600. #define DP_TEST_CRC_G_Y 0x242
  601. #define DP_TEST_CRC_B_CB 0x244
  602. #define DP_TEST_SINK_MISC 0x246
  603. # define DP_TEST_CRC_SUPPORTED (1 << 5)
  604. # define DP_TEST_COUNT_MASK 0xf
  605. #define DP_PHY_TEST_PATTERN 0x248
  606. # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
  607. # define DP_PHY_TEST_PATTERN_NONE 0x0
  608. # define DP_PHY_TEST_PATTERN_D10_2 0x1
  609. # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
  610. # define DP_PHY_TEST_PATTERN_PRBS7 0x3
  611. # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
  612. # define DP_PHY_TEST_PATTERN_CP2520 0x5
  613. #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
  614. #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
  615. #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
  616. #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
  617. #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
  618. #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
  619. #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
  620. #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
  621. #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
  622. #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
  623. #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
  624. #define DP_TEST_RESPONSE 0x260
  625. # define DP_TEST_ACK (1 << 0)
  626. # define DP_TEST_NAK (1 << 1)
  627. # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
  628. #define DP_TEST_EDID_CHECKSUM 0x261
  629. #define DP_TEST_SINK 0x270
  630. # define DP_TEST_SINK_START (1 << 0)
  631. #define DP_TEST_AUDIO_MODE 0x271
  632. #define DP_TEST_AUDIO_PATTERN_TYPE 0x272
  633. #define DP_TEST_AUDIO_PERIOD_CH1 0x273
  634. #define DP_TEST_AUDIO_PERIOD_CH2 0x274
  635. #define DP_TEST_AUDIO_PERIOD_CH3 0x275
  636. #define DP_TEST_AUDIO_PERIOD_CH4 0x276
  637. #define DP_TEST_AUDIO_PERIOD_CH5 0x277
  638. #define DP_TEST_AUDIO_PERIOD_CH6 0x278
  639. #define DP_TEST_AUDIO_PERIOD_CH7 0x279
  640. #define DP_TEST_AUDIO_PERIOD_CH8 0x27A
  641. #define DP_FEC_STATUS 0x280 /* 1.4 */
  642. # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
  643. # define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
  644. #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
  645. #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
  646. # define DP_FEC_ERROR_COUNT_MASK 0x7F
  647. # define DP_FEC_ERR_COUNT_VALID (1 << 7)
  648. #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
  649. # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
  650. # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
  651. #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
  652. /* up to ID_SLOT_63 at 0x2ff */
  653. #define DP_SOURCE_OUI 0x300
  654. #define DP_SINK_OUI 0x400
  655. #define DP_BRANCH_OUI 0x500
  656. #define DP_BRANCH_ID 0x503
  657. #define DP_BRANCH_REVISION_START 0x509
  658. #define DP_BRANCH_HW_REV 0x509
  659. #define DP_BRANCH_SW_REV 0x50A
  660. #define DP_SET_POWER 0x600
  661. # define DP_SET_POWER_D0 0x1
  662. # define DP_SET_POWER_D3 0x2
  663. # define DP_SET_POWER_MASK 0x3
  664. # define DP_SET_POWER_D3_AUX_ON 0x5
  665. #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
  666. # define DP_EDP_11 0x00
  667. # define DP_EDP_12 0x01
  668. # define DP_EDP_13 0x02
  669. # define DP_EDP_14 0x03
  670. # define DP_EDP_14a 0x04 /* eDP 1.4a */
  671. # define DP_EDP_14b 0x05 /* eDP 1.4b */
  672. #define DP_EDP_GENERAL_CAP_1 0x701
  673. # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
  674. # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
  675. # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
  676. # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
  677. # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
  678. # define DP_EDP_FRC_ENABLE_CAP (1 << 5)
  679. # define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
  680. # define DP_EDP_SET_POWER_CAP (1 << 7)
  681. #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
  682. # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
  683. # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
  684. # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
  685. # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
  686. # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
  687. # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
  688. # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
  689. # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
  690. #define DP_EDP_GENERAL_CAP_2 0x703
  691. # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
  692. #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
  693. # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
  694. # define DP_EDP_X_REGION_CAP_SHIFT 0
  695. # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
  696. # define DP_EDP_Y_REGION_CAP_SHIFT 4
  697. #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
  698. # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
  699. # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
  700. # define DP_EDP_FRC_ENABLE (1 << 2)
  701. # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
  702. # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
  703. #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
  704. # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
  705. # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
  706. # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
  707. # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
  708. # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
  709. # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
  710. # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
  711. # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
  712. # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
  713. # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
  714. #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
  715. #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
  716. #define DP_EDP_PWMGEN_BIT_COUNT 0x724
  717. #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
  718. #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
  719. # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
  720. #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
  721. #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
  722. # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
  723. #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
  724. #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
  725. #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
  726. #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
  727. #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
  728. #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
  729. #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
  730. #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
  731. #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
  732. #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
  733. #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
  734. #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
  735. #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
  736. #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
  737. #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
  738. /* 0-5 sink count */
  739. # define DP_SINK_COUNT_CP_READY (1 << 6)
  740. #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
  741. #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
  742. # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
  743. # define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
  744. # define DP_CEC_IRQ (1 << 2)
  745. #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
  746. #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
  747. # define DP_PSR_LINK_CRC_ERROR (1 << 0)
  748. # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
  749. # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
  750. #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
  751. # define DP_PSR_CAPS_CHANGE (1 << 0)
  752. #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
  753. # define DP_PSR_SINK_INACTIVE 0
  754. # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
  755. # define DP_PSR_SINK_ACTIVE_RFB 2
  756. # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
  757. # define DP_PSR_SINK_ACTIVE_RESYNC 4
  758. # define DP_PSR_SINK_INTERNAL_ERROR 7
  759. # define DP_PSR_SINK_STATE_MASK 0x07
  760. #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
  761. # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
  762. # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
  763. # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
  764. # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
  765. #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
  766. # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
  767. # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
  768. # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
  769. # define DP_SU_VALID (1 << 3) /* eDP 1.4 */
  770. # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
  771. # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
  772. # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
  773. #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
  774. # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
  775. #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
  776. #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
  777. #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
  778. #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
  779. #define DP_DP13_DPCD_REV 0x2200
  780. #define DP_DP13_MAX_LINK_RATE 0x2201
  781. #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
  782. # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
  783. # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
  784. # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
  785. # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
  786. # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
  787. # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
  788. # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
  789. # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
  790. /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
  791. #define DP_CEC_TUNNELING_CAPABILITY 0x3000
  792. # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
  793. # define DP_CEC_SNOOPING_CAPABLE (1 << 1)
  794. # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
  795. #define DP_CEC_TUNNELING_CONTROL 0x3001
  796. # define DP_CEC_TUNNELING_ENABLE (1 << 0)
  797. # define DP_CEC_SNOOPING_ENABLE (1 << 1)
  798. #define DP_CEC_RX_MESSAGE_INFO 0x3002
  799. # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
  800. # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
  801. # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
  802. # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
  803. # define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
  804. # define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
  805. #define DP_CEC_TX_MESSAGE_INFO 0x3003
  806. # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
  807. # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
  808. # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
  809. # define DP_CEC_TX_RETRY_COUNT_SHIFT 4
  810. # define DP_CEC_TX_MESSAGE_SEND (1 << 7)
  811. #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
  812. # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
  813. # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
  814. # define DP_CEC_TX_MESSAGE_SENT (1 << 4)
  815. # define DP_CEC_TX_LINE_ERROR (1 << 5)
  816. # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
  817. # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
  818. #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
  819. # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
  820. # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
  821. # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
  822. # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
  823. # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
  824. # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
  825. # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
  826. # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
  827. #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
  828. # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
  829. # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
  830. # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
  831. # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
  832. # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
  833. # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
  834. # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
  835. # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
  836. #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
  837. #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
  838. #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
  839. #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
  840. # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
  841. #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
  842. # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
  843. # define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */
  844. # define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */
  845. # define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */
  846. #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
  847. # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
  848. #define DP_AUX_HDCP_BKSV 0x68000
  849. #define DP_AUX_HDCP_RI_PRIME 0x68005
  850. #define DP_AUX_HDCP_AKSV 0x68007
  851. #define DP_AUX_HDCP_AN 0x6800C
  852. #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
  853. #define DP_AUX_HDCP_BCAPS 0x68028
  854. # define DP_BCAPS_REPEATER_PRESENT BIT(1)
  855. # define DP_BCAPS_HDCP_CAPABLE BIT(0)
  856. #define DP_AUX_HDCP_BSTATUS 0x68029
  857. # define DP_BSTATUS_REAUTH_REQ BIT(3)
  858. # define DP_BSTATUS_LINK_FAILURE BIT(2)
  859. # define DP_BSTATUS_R0_PRIME_READY BIT(1)
  860. # define DP_BSTATUS_READY BIT(0)
  861. #define DP_AUX_HDCP_BINFO 0x6802A
  862. #define DP_AUX_HDCP_KSV_FIFO 0x6802C
  863. #define DP_AUX_HDCP_AINFO 0x6803B
  864. /* DP HDCP2.2 parameter offsets in DPCD address space */
  865. #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
  866. #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
  867. #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
  868. #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
  869. #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
  870. #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
  871. #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
  872. #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
  873. #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
  874. #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
  875. #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
  876. #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
  877. #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
  878. #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
  879. #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
  880. #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
  881. #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
  882. #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
  883. #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
  884. #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
  885. #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
  886. #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
  887. #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
  888. #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
  889. #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
  890. #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
  891. /* Link Training (LT)-tunable PHY Repeaters */
  892. #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
  893. #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
  894. #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
  895. #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
  896. #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
  897. #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
  898. #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
  899. #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
  900. #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
  901. #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
  902. #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
  903. #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
  904. #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
  905. #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
  906. #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
  907. #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
  908. #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
  909. #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
  910. #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
  911. #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
  912. #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
  913. #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
  914. #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
  915. #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
  916. #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
  917. #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
  918. /* Repeater modes */
  919. #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
  920. #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
  921. /* DP HDCP message start offsets in DPCD address space */
  922. #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
  923. #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
  924. #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
  925. #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
  926. #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
  927. #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
  928. DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
  929. #define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
  930. #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
  931. #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
  932. #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
  933. #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
  934. #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
  935. #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
  936. #define HDCP_2_2_DP_RXSTATUS_LEN 1
  937. #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
  938. #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
  939. #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
  940. #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
  941. #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
  942. /* DP 1.2 Sideband message defines */
  943. /* peer device type - DP 1.2a Table 2-92 */
  944. #define DP_PEER_DEVICE_NONE 0x0
  945. #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
  946. #define DP_PEER_DEVICE_MST_BRANCHING 0x2
  947. #define DP_PEER_DEVICE_SST_SINK 0x3
  948. #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
  949. /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
  950. #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
  951. #define DP_LINK_ADDRESS 0x01
  952. #define DP_CONNECTION_STATUS_NOTIFY 0x02
  953. #define DP_ENUM_PATH_RESOURCES 0x10
  954. #define DP_ALLOCATE_PAYLOAD 0x11
  955. #define DP_QUERY_PAYLOAD 0x12
  956. #define DP_RESOURCE_STATUS_NOTIFY 0x13
  957. #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
  958. #define DP_REMOTE_DPCD_READ 0x20
  959. #define DP_REMOTE_DPCD_WRITE 0x21
  960. #define DP_REMOTE_I2C_READ 0x22
  961. #define DP_REMOTE_I2C_WRITE 0x23
  962. #define DP_POWER_UP_PHY 0x24
  963. #define DP_POWER_DOWN_PHY 0x25
  964. #define DP_SINK_EVENT_NOTIFY 0x30
  965. #define DP_QUERY_STREAM_ENC_STATUS 0x38
  966. #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
  967. #define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1
  968. #define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2
  969. /* DP 1.2 MST sideband reply types */
  970. #define DP_SIDEBAND_REPLY_ACK 0x00
  971. #define DP_SIDEBAND_REPLY_NAK 0x01
  972. /* DP 1.2 MST sideband nak reasons - table 2.84 */
  973. #define DP_NAK_WRITE_FAILURE 0x01
  974. #define DP_NAK_INVALID_READ 0x02
  975. #define DP_NAK_CRC_FAILURE 0x03
  976. #define DP_NAK_BAD_PARAM 0x04
  977. #define DP_NAK_DEFER 0x05
  978. #define DP_NAK_LINK_FAILURE 0x06
  979. #define DP_NAK_NO_RESOURCES 0x07
  980. #define DP_NAK_DPCD_FAIL 0x08
  981. #define DP_NAK_I2C_NAK 0x09
  982. #define DP_NAK_ALLOCATE_FAIL 0x0a
  983. #define MODE_I2C_START 1
  984. #define MODE_I2C_WRITE 2
  985. #define MODE_I2C_READ 4
  986. #define MODE_I2C_STOP 8
  987. /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
  988. #define DP_MST_PHYSICAL_PORT_0 0
  989. #define DP_MST_LOGICAL_PORT_0 8
  990. #define DP_LINK_CONSTANT_N_VALUE 0x8000
  991. #define DP_LINK_STATUS_SIZE 6
  992. bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  993. int lane_count);
  994. bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  995. int lane_count);
  996. u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
  997. int lane);
  998. u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
  999. int lane);
  1000. u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
  1001. unsigned int lane);
  1002. #define DP_BRANCH_OUI_HEADER_SIZE 0xc
  1003. #define DP_RECEIVER_CAP_SIZE 0xf
  1004. #define DP_DSC_RECEIVER_CAP_SIZE 0xf
  1005. #define EDP_PSR_RECEIVER_CAP_SIZE 2
  1006. #define EDP_DISPLAY_CTL_CAP_SIZE 3
  1007. void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
  1008. void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
  1009. u8 drm_dp_link_rate_to_bw_code(int link_rate);
  1010. int drm_dp_bw_code_to_link_rate(u8 link_bw);
  1011. #define DP_SDP_AUDIO_TIMESTAMP 0x01
  1012. #define DP_SDP_AUDIO_STREAM 0x02
  1013. #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
  1014. #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
  1015. #define DP_SDP_ISRC 0x06 /* DP 1.2 */
  1016. #define DP_SDP_VSC 0x07 /* DP 1.2 */
  1017. #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
  1018. #define DP_SDP_PPS 0x10 /* DP 1.4 */
  1019. #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
  1020. #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
  1021. /* 0x80+ CEA-861 infoframe types */
  1022. /**
  1023. * struct dp_sdp_header - DP secondary data packet header
  1024. * @HB0: Secondary Data Packet ID
  1025. * @HB1: Secondary Data Packet Type
  1026. * @HB2: Secondary Data Packet Specific header, Byte 0
  1027. * @HB3: Secondary Data packet Specific header, Byte 1
  1028. */
  1029. struct dp_sdp_header {
  1030. u8 HB0;
  1031. u8 HB1;
  1032. u8 HB2;
  1033. u8 HB3;
  1034. } __packed;
  1035. #define EDP_SDP_HEADER_REVISION_MASK 0x1F
  1036. #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
  1037. #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
  1038. /**
  1039. * struct dp_sdp - DP secondary data packet
  1040. * @sdp_header: DP secondary data packet header
  1041. * @db: DP secondaray data packet data blocks
  1042. * VSC SDP Payload for PSR
  1043. * db[0]: Stereo Interface
  1044. * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
  1045. * db[2]: CRC value bits 7:0 of the R or Cr component
  1046. * db[3]: CRC value bits 15:8 of the R or Cr component
  1047. * db[4]: CRC value bits 7:0 of the G or Y component
  1048. * db[5]: CRC value bits 15:8 of the G or Y component
  1049. * db[6]: CRC value bits 7:0 of the B or Cb component
  1050. * db[7]: CRC value bits 15:8 of the B or Cb component
  1051. * db[8] - db[31]: Reserved
  1052. * VSC SDP Payload for Pixel Encoding/Colorimetry Format
  1053. * db[0] - db[15]: Reserved
  1054. * db[16]: Pixel Encoding and Colorimetry Formats
  1055. * db[17]: Dynamic Range and Component Bit Depth
  1056. * db[18]: Content Type
  1057. * db[19] - db[31]: Reserved
  1058. */
  1059. struct dp_sdp {
  1060. struct dp_sdp_header sdp_header;
  1061. u8 db[32];
  1062. } __packed;
  1063. #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
  1064. #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
  1065. #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
  1066. /**
  1067. * enum dp_pixelformat - drm DP Pixel encoding formats
  1068. *
  1069. * This enum is used to indicate DP VSC SDP Pixel encoding formats.
  1070. * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
  1071. * DB18]
  1072. *
  1073. * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
  1074. * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
  1075. * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
  1076. * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
  1077. * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
  1078. * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
  1079. * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
  1080. */
  1081. enum dp_pixelformat {
  1082. DP_PIXELFORMAT_RGB = 0,
  1083. DP_PIXELFORMAT_YUV444 = 0x1,
  1084. DP_PIXELFORMAT_YUV422 = 0x2,
  1085. DP_PIXELFORMAT_YUV420 = 0x3,
  1086. DP_PIXELFORMAT_Y_ONLY = 0x4,
  1087. DP_PIXELFORMAT_RAW = 0x5,
  1088. DP_PIXELFORMAT_RESERVED = 0x6,
  1089. };
  1090. /**
  1091. * enum dp_colorimetry - drm DP Colorimetry formats
  1092. *
  1093. * This enum is used to indicate DP VSC SDP Colorimetry formats.
  1094. * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
  1095. * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
  1096. *
  1097. * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
  1098. * ITU-R BT.601 colorimetry format
  1099. * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
  1100. * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
  1101. * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
  1102. * (scRGB (IEC 61966-2-2)) colorimetry format
  1103. * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
  1104. * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
  1105. * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
  1106. * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
  1107. * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
  1108. * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
  1109. * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
  1110. * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
  1111. * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
  1112. * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
  1113. */
  1114. enum dp_colorimetry {
  1115. DP_COLORIMETRY_DEFAULT = 0,
  1116. DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
  1117. DP_COLORIMETRY_BT709_YCC = 0x1,
  1118. DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
  1119. DP_COLORIMETRY_XVYCC_601 = 0x2,
  1120. DP_COLORIMETRY_OPRGB = 0x3,
  1121. DP_COLORIMETRY_XVYCC_709 = 0x3,
  1122. DP_COLORIMETRY_DCI_P3_RGB = 0x4,
  1123. DP_COLORIMETRY_SYCC_601 = 0x4,
  1124. DP_COLORIMETRY_RGB_CUSTOM = 0x5,
  1125. DP_COLORIMETRY_OPYCC_601 = 0x5,
  1126. DP_COLORIMETRY_BT2020_RGB = 0x6,
  1127. DP_COLORIMETRY_BT2020_CYCC = 0x6,
  1128. DP_COLORIMETRY_BT2020_YCC = 0x7,
  1129. };
  1130. /**
  1131. * enum dp_dynamic_range - drm DP Dynamic Range
  1132. *
  1133. * This enum is used to indicate DP VSC SDP Dynamic Range.
  1134. * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
  1135. * DB18]
  1136. *
  1137. * @DP_DYNAMIC_RANGE_VESA: VESA range
  1138. * @DP_DYNAMIC_RANGE_CTA: CTA range
  1139. */
  1140. enum dp_dynamic_range {
  1141. DP_DYNAMIC_RANGE_VESA = 0,
  1142. DP_DYNAMIC_RANGE_CTA = 1,
  1143. };
  1144. /**
  1145. * enum dp_content_type - drm DP Content Type
  1146. *
  1147. * This enum is used to indicate DP VSC SDP Content Types.
  1148. * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
  1149. * DB18]
  1150. * CTA-861-G defines content types and expected processing by a sink device
  1151. *
  1152. * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
  1153. * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
  1154. * @DP_CONTENT_TYPE_PHOTO: Photo type
  1155. * @DP_CONTENT_TYPE_VIDEO: Video type
  1156. * @DP_CONTENT_TYPE_GAME: Game type
  1157. */
  1158. enum dp_content_type {
  1159. DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
  1160. DP_CONTENT_TYPE_GRAPHICS = 0x01,
  1161. DP_CONTENT_TYPE_PHOTO = 0x02,
  1162. DP_CONTENT_TYPE_VIDEO = 0x03,
  1163. DP_CONTENT_TYPE_GAME = 0x04,
  1164. };
  1165. /**
  1166. * struct drm_dp_vsc_sdp - drm DP VSC SDP
  1167. *
  1168. * This structure represents a DP VSC SDP of drm
  1169. * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
  1170. * [Table 2-117: VSC SDP Payload for DB16 through DB18]
  1171. *
  1172. * @sdp_type: secondary-data packet type
  1173. * @revision: revision number
  1174. * @length: number of valid data bytes
  1175. * @pixelformat: pixel encoding format
  1176. * @colorimetry: colorimetry format
  1177. * @bpc: bit per color
  1178. * @dynamic_range: dynamic range information
  1179. * @content_type: CTA-861-G defines content types and expected processing by a sink device
  1180. */
  1181. struct drm_dp_vsc_sdp {
  1182. unsigned char sdp_type;
  1183. unsigned char revision;
  1184. unsigned char length;
  1185. enum dp_pixelformat pixelformat;
  1186. enum dp_colorimetry colorimetry;
  1187. int bpc;
  1188. enum dp_dynamic_range dynamic_range;
  1189. enum dp_content_type content_type;
  1190. };
  1191. void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
  1192. const struct drm_dp_vsc_sdp *vsc);
  1193. int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
  1194. static inline int
  1195. drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1196. {
  1197. return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
  1198. }
  1199. static inline u8
  1200. drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1201. {
  1202. return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
  1203. }
  1204. static inline bool
  1205. drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1206. {
  1207. return dpcd[DP_DPCD_REV] >= 0x11 &&
  1208. (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
  1209. }
  1210. static inline bool
  1211. drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1212. {
  1213. return dpcd[DP_DPCD_REV] >= 0x11 &&
  1214. (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
  1215. }
  1216. static inline bool
  1217. drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1218. {
  1219. return dpcd[DP_DPCD_REV] >= 0x12 &&
  1220. dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
  1221. }
  1222. static inline bool
  1223. drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1224. {
  1225. return dpcd[DP_DPCD_REV] >= 0x14 &&
  1226. dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
  1227. }
  1228. static inline u8
  1229. drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1230. {
  1231. return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
  1232. DP_TRAINING_PATTERN_MASK;
  1233. }
  1234. static inline bool
  1235. drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1236. {
  1237. return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
  1238. }
  1239. /* DP/eDP DSC support */
  1240. u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
  1241. bool is_edp);
  1242. u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
  1243. int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
  1244. u8 dsc_bpc[3]);
  1245. static inline bool
  1246. drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
  1247. {
  1248. return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
  1249. DP_DSC_DECOMPRESSION_IS_SUPPORTED;
  1250. }
  1251. static inline u16
  1252. drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
  1253. {
  1254. return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
  1255. (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
  1256. DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
  1257. DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
  1258. }
  1259. static inline u32
  1260. drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
  1261. {
  1262. /* Max Slicewidth = Number of Pixels * 320 */
  1263. return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
  1264. DP_DSC_SLICE_WIDTH_MULTIPLIER;
  1265. }
  1266. /* Forward Error Correction Support on DP 1.4 */
  1267. static inline bool
  1268. drm_dp_sink_supports_fec(const u8 fec_capable)
  1269. {
  1270. return fec_capable & DP_FEC_CAPABLE;
  1271. }
  1272. static inline bool
  1273. drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1274. {
  1275. return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
  1276. }
  1277. static inline bool
  1278. drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1279. {
  1280. return dpcd[DP_EDP_CONFIGURATION_CAP] &
  1281. DP_ALTERNATE_SCRAMBLER_RESET_CAP;
  1282. }
  1283. /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
  1284. static inline bool
  1285. drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  1286. {
  1287. return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
  1288. DP_MSA_TIMING_PAR_IGNORED;
  1289. }
  1290. /*
  1291. * DisplayPort AUX channel
  1292. */
  1293. /**
  1294. * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
  1295. * @address: address of the (first) register to access
  1296. * @request: contains the type of transaction (see DP_AUX_* macros)
  1297. * @reply: upon completion, contains the reply type of the transaction
  1298. * @buffer: pointer to a transmission or reception buffer
  1299. * @size: size of @buffer
  1300. */
  1301. struct drm_dp_aux_msg {
  1302. unsigned int address;
  1303. u8 request;
  1304. u8 reply;
  1305. void *buffer;
  1306. size_t size;
  1307. };
  1308. struct cec_adapter;
  1309. struct edid;
  1310. struct drm_connector;
  1311. /**
  1312. * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
  1313. * @lock: mutex protecting this struct
  1314. * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
  1315. * @connector: the connector this CEC adapter is associated with
  1316. * @unregister_work: unregister the CEC adapter
  1317. */
  1318. struct drm_dp_aux_cec {
  1319. struct mutex lock;
  1320. struct cec_adapter *adap;
  1321. struct drm_connector *connector;
  1322. struct delayed_work unregister_work;
  1323. };
  1324. /**
  1325. * struct drm_dp_aux - DisplayPort AUX channel
  1326. * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
  1327. * @ddc: I2C adapter that can be used for I2C-over-AUX communication
  1328. * @dev: pointer to struct device that is the parent for this AUX channel
  1329. * @crtc: backpointer to the crtc that is currently using this AUX channel
  1330. * @hw_mutex: internal mutex used for locking transfers
  1331. * @crc_work: worker that captures CRCs for each frame
  1332. * @crc_count: counter of captured frame CRCs
  1333. * @transfer: transfers a message representing a single AUX transaction
  1334. *
  1335. * The .dev field should be set to a pointer to the device that implements
  1336. * the AUX channel.
  1337. *
  1338. * The .name field may be used to specify the name of the I2C adapter. If set to
  1339. * NULL, dev_name() of .dev will be used.
  1340. *
  1341. * Drivers provide a hardware-specific implementation of how transactions
  1342. * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
  1343. * structure describing the transaction is passed into this function. Upon
  1344. * success, the implementation should return the number of payload bytes
  1345. * that were transferred, or a negative error-code on failure. Helpers
  1346. * propagate errors from the .transfer() function, with the exception of
  1347. * the -EBUSY error, which causes a transaction to be retried. On a short,
  1348. * helpers will return -EPROTO to make it simpler to check for failure.
  1349. *
  1350. * An AUX channel can also be used to transport I2C messages to a sink. A
  1351. * typical application of that is to access an EDID that's present in the
  1352. * sink device. The .transfer() function can also be used to execute such
  1353. * transactions. The drm_dp_aux_register() function registers an I2C
  1354. * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
  1355. * should call drm_dp_aux_unregister() to remove the I2C adapter.
  1356. * The I2C adapter uses long transfers by default; if a partial response is
  1357. * received, the adapter will drop down to the size given by the partial
  1358. * response for this transaction only.
  1359. *
  1360. * Note that the aux helper code assumes that the .transfer() function
  1361. * only modifies the reply field of the drm_dp_aux_msg structure. The
  1362. * retry logic and i2c helpers assume this is the case.
  1363. */
  1364. struct drm_dp_aux {
  1365. const char *name;
  1366. struct i2c_adapter ddc;
  1367. struct device *dev;
  1368. struct drm_crtc *crtc;
  1369. struct mutex hw_mutex;
  1370. struct work_struct crc_work;
  1371. u8 crc_count;
  1372. ssize_t (*transfer)(struct drm_dp_aux *aux,
  1373. struct drm_dp_aux_msg *msg);
  1374. /**
  1375. * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
  1376. */
  1377. unsigned i2c_nack_count;
  1378. /**
  1379. * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
  1380. */
  1381. unsigned i2c_defer_count;
  1382. /**
  1383. * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
  1384. */
  1385. struct drm_dp_aux_cec cec;
  1386. /**
  1387. * @is_remote: Is this AUX CH actually using sideband messaging.
  1388. */
  1389. bool is_remote;
  1390. };
  1391. ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
  1392. void *buffer, size_t size);
  1393. ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
  1394. void *buffer, size_t size);
  1395. /**
  1396. * drm_dp_dpcd_readb() - read a single byte from the DPCD
  1397. * @aux: DisplayPort AUX channel
  1398. * @offset: address of the register to read
  1399. * @valuep: location where the value of the register will be stored
  1400. *
  1401. * Returns the number of bytes transferred (1) on success, or a negative
  1402. * error code on failure.
  1403. */
  1404. static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
  1405. unsigned int offset, u8 *valuep)
  1406. {
  1407. return drm_dp_dpcd_read(aux, offset, valuep, 1);
  1408. }
  1409. /**
  1410. * drm_dp_dpcd_writeb() - write a single byte to the DPCD
  1411. * @aux: DisplayPort AUX channel
  1412. * @offset: address of the register to write
  1413. * @value: value to write to the register
  1414. *
  1415. * Returns the number of bytes transferred (1) on success, or a negative
  1416. * error code on failure.
  1417. */
  1418. static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
  1419. unsigned int offset, u8 value)
  1420. {
  1421. return drm_dp_dpcd_write(aux, offset, &value, 1);
  1422. }
  1423. int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
  1424. u8 dpcd[DP_RECEIVER_CAP_SIZE]);
  1425. int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
  1426. u8 status[DP_LINK_STATUS_SIZE]);
  1427. bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
  1428. u8 real_edid_checksum);
  1429. int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
  1430. const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1431. u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
  1432. bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1433. const u8 port_cap[4], u8 type);
  1434. bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1435. const u8 port_cap[4],
  1436. const struct edid *edid);
  1437. int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1438. const u8 port_cap[4]);
  1439. int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1440. const u8 port_cap[4],
  1441. const struct edid *edid);
  1442. int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1443. const u8 port_cap[4],
  1444. const struct edid *edid);
  1445. int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1446. const u8 port_cap[4],
  1447. const struct edid *edid);
  1448. bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1449. const u8 port_cap[4]);
  1450. bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1451. const u8 port_cap[4]);
  1452. struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
  1453. const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1454. const u8 port_cap[4]);
  1455. int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
  1456. void drm_dp_downstream_debug(struct seq_file *m,
  1457. const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1458. const u8 port_cap[4],
  1459. const struct edid *edid,
  1460. struct drm_dp_aux *aux);
  1461. enum drm_mode_subconnector
  1462. drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1463. const u8 port_cap[4]);
  1464. void drm_dp_set_subconnector_property(struct drm_connector *connector,
  1465. enum drm_connector_status status,
  1466. const u8 *dpcd,
  1467. const u8 port_cap[4]);
  1468. struct drm_dp_desc;
  1469. bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
  1470. const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  1471. const struct drm_dp_desc *desc);
  1472. int drm_dp_read_sink_count(struct drm_dp_aux *aux);
  1473. void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
  1474. void drm_dp_aux_init(struct drm_dp_aux *aux);
  1475. int drm_dp_aux_register(struct drm_dp_aux *aux);
  1476. void drm_dp_aux_unregister(struct drm_dp_aux *aux);
  1477. int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
  1478. int drm_dp_stop_crc(struct drm_dp_aux *aux);
  1479. struct drm_dp_dpcd_ident {
  1480. u8 oui[3];
  1481. u8 device_id[6];
  1482. u8 hw_rev;
  1483. u8 sw_major_rev;
  1484. u8 sw_minor_rev;
  1485. } __packed;
  1486. /**
  1487. * struct drm_dp_desc - DP branch/sink device descriptor
  1488. * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
  1489. * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
  1490. */
  1491. struct drm_dp_desc {
  1492. struct drm_dp_dpcd_ident ident;
  1493. u32 quirks;
  1494. };
  1495. int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
  1496. bool is_branch);
  1497. u32 drm_dp_get_edid_quirks(const struct edid *edid);
  1498. /**
  1499. * enum drm_dp_quirk - Display Port sink/branch device specific quirks
  1500. *
  1501. * Display Port sink and branch devices in the wild have a variety of bugs, try
  1502. * to collect them here. The quirks are shared, but it's up to the drivers to
  1503. * implement workarounds for them. Note that because some devices have
  1504. * unreliable OUIDs, the EDID of sinks should also be checked for quirks using
  1505. * drm_dp_get_edid_quirks().
  1506. */
  1507. enum drm_dp_quirk {
  1508. /**
  1509. * @DP_DPCD_QUIRK_CONSTANT_N:
  1510. *
  1511. * The device requires main link attributes Mvid and Nvid to be limited
  1512. * to 16 bits. So will give a constant value (0x8000) for compatability.
  1513. */
  1514. DP_DPCD_QUIRK_CONSTANT_N,
  1515. /**
  1516. * @DP_DPCD_QUIRK_NO_PSR:
  1517. *
  1518. * The device does not support PSR even if reports that it supports or
  1519. * driver still need to implement proper handling for such device.
  1520. */
  1521. DP_DPCD_QUIRK_NO_PSR,
  1522. /**
  1523. * @DP_DPCD_QUIRK_NO_SINK_COUNT:
  1524. *
  1525. * The device does not set SINK_COUNT to a non-zero value.
  1526. * The driver should ignore SINK_COUNT during detection. Note that
  1527. * drm_dp_read_sink_count_cap() automatically checks for this quirk.
  1528. */
  1529. DP_DPCD_QUIRK_NO_SINK_COUNT,
  1530. /**
  1531. * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
  1532. *
  1533. * The device supports MST DSC despite not supporting Virtual DPCD.
  1534. * The DSC caps can be read from the physical aux instead.
  1535. */
  1536. DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
  1537. /**
  1538. * @DP_QUIRK_FORCE_DPCD_BACKLIGHT:
  1539. *
  1540. * The device is telling the truth when it says that it uses DPCD
  1541. * backlight controls, even if the system's firmware disagrees. This
  1542. * quirk should be checked against both the ident and panel EDID.
  1543. * When present, the driver should honor the DPCD backlight
  1544. * capabilities advertised.
  1545. */
  1546. DP_QUIRK_FORCE_DPCD_BACKLIGHT,
  1547. /**
  1548. * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
  1549. *
  1550. * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
  1551. * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
  1552. */
  1553. DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
  1554. };
  1555. /**
  1556. * drm_dp_has_quirk() - does the DP device have a specific quirk
  1557. * @desc: Device descriptor filled by drm_dp_read_desc()
  1558. * @edid_quirks: Optional quirk bitmask filled by drm_dp_get_edid_quirks()
  1559. * @quirk: Quirk to query for
  1560. *
  1561. * Return true if DP device identified by @desc has @quirk.
  1562. */
  1563. static inline bool
  1564. drm_dp_has_quirk(const struct drm_dp_desc *desc, u32 edid_quirks,
  1565. enum drm_dp_quirk quirk)
  1566. {
  1567. return (desc->quirks | edid_quirks) & BIT(quirk);
  1568. }
  1569. #ifdef CONFIG_DRM_DP_CEC
  1570. void drm_dp_cec_irq(struct drm_dp_aux *aux);
  1571. void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
  1572. struct drm_connector *connector);
  1573. void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
  1574. void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
  1575. void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
  1576. #else
  1577. static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
  1578. {
  1579. }
  1580. static inline void
  1581. drm_dp_cec_register_connector(struct drm_dp_aux *aux,
  1582. struct drm_connector *connector)
  1583. {
  1584. }
  1585. static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
  1586. {
  1587. }
  1588. static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
  1589. const struct edid *edid)
  1590. {
  1591. }
  1592. static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
  1593. {
  1594. }
  1595. #endif
  1596. /**
  1597. * struct drm_dp_phy_test_params - DP Phy Compliance parameters
  1598. * @link_rate: Requested Link rate from DPCD 0x219
  1599. * @num_lanes: Number of lanes requested by sing through DPCD 0x220
  1600. * @phy_pattern: DP Phy test pattern from DPCD 0x248
  1601. * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
  1602. * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
  1603. * @enhanced_frame_cap: flag for enhanced frame capability.
  1604. */
  1605. struct drm_dp_phy_test_params {
  1606. int link_rate;
  1607. u8 num_lanes;
  1608. u8 phy_pattern;
  1609. u8 hbr2_reset[2];
  1610. u8 custom80[10];
  1611. bool enhanced_frame_cap;
  1612. };
  1613. int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
  1614. struct drm_dp_phy_test_params *data);
  1615. int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
  1616. struct drm_dp_phy_test_params *data, u8 dp_rev);
  1617. #endif /* _DRM_DP_HELPER_H_ */