drm_cache.h 2.9 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273
  1. /**************************************************************************
  2. *
  3. * Copyright 2009 Red Hat Inc.
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. *
  27. **************************************************************************/
  28. /*
  29. * Authors:
  30. * Dave Airlie <airlied@redhat.com>
  31. */
  32. #ifndef _DRM_CACHE_H_
  33. #define _DRM_CACHE_H_
  34. #include <linux/scatterlist.h>
  35. void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
  36. void drm_clflush_sg(struct sg_table *st);
  37. void drm_clflush_virt_range(void *addr, unsigned long length);
  38. bool drm_need_swiotlb(int dma_bits);
  39. static inline bool drm_arch_can_wc_memory(void)
  40. {
  41. #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
  42. return false;
  43. #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON64)
  44. return false;
  45. #elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
  46. /*
  47. * The DRM driver stack is designed to work with cache coherent devices
  48. * only, but permits an optimization to be enabled in some cases, where
  49. * for some buffers, both the CPU and the GPU use uncached mappings,
  50. * removing the need for DMA snooping and allocation in the CPU caches.
  51. *
  52. * The use of uncached GPU mappings relies on the correct implementation
  53. * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU
  54. * will use cached mappings nonetheless. On x86 platforms, this does not
  55. * seem to matter, as uncached CPU mappings will snoop the caches in any
  56. * case. However, on ARM and arm64, enabling this optimization on a
  57. * platform where NoSnoop is ignored results in loss of coherency, which
  58. * breaks correct operation of the device. Since we have no way of
  59. * detecting whether NoSnoop works or not, just disable this
  60. * optimization entirely for ARM and arm64.
  61. */
  62. return false;
  63. #else
  64. return true;
  65. #endif
  66. }
  67. #endif