zx2967_wdt.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * watchdog driver for ZTE's zx2967 family
  4. *
  5. * Copyright (C) 2017 ZTE Ltd.
  6. *
  7. * Author: Baoyou Xie <baoyou.xie@linaro.org>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/module.h>
  13. #include <linux/of_address.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regmap.h>
  16. #include <linux/reset.h>
  17. #include <linux/watchdog.h>
  18. #define ZX2967_WDT_CFG_REG 0x4
  19. #define ZX2967_WDT_LOAD_REG 0x8
  20. #define ZX2967_WDT_REFRESH_REG 0x18
  21. #define ZX2967_WDT_START_REG 0x1c
  22. #define ZX2967_WDT_REFRESH_MASK GENMASK(5, 0)
  23. #define ZX2967_WDT_CFG_DIV(n) ((((n) & 0xff) - 1) << 8)
  24. #define ZX2967_WDT_START_EN 0x1
  25. /*
  26. * Hardware magic number.
  27. * When watchdog reg is written, the lowest 16 bits are valid, but
  28. * the highest 16 bits should be always this number.
  29. */
  30. #define ZX2967_WDT_WRITEKEY (0x1234 << 16)
  31. #define ZX2967_WDT_VAL_MASK GENMASK(15, 0)
  32. #define ZX2967_WDT_DIV_DEFAULT 16
  33. #define ZX2967_WDT_DEFAULT_TIMEOUT 32
  34. #define ZX2967_WDT_MIN_TIMEOUT 1
  35. #define ZX2967_WDT_MAX_TIMEOUT 524
  36. #define ZX2967_WDT_MAX_COUNT 0xffff
  37. #define ZX2967_WDT_CLK_FREQ 0x8000
  38. #define ZX2967_WDT_FLAG_REBOOT_MON BIT(0)
  39. struct zx2967_wdt {
  40. struct watchdog_device wdt_device;
  41. void __iomem *reg_base;
  42. struct clk *clock;
  43. };
  44. static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg)
  45. {
  46. return readl_relaxed(wdt->reg_base + reg);
  47. }
  48. static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val)
  49. {
  50. writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg);
  51. }
  52. static void zx2967_wdt_refresh(struct zx2967_wdt *wdt)
  53. {
  54. u32 val;
  55. val = zx2967_wdt_readl(wdt, ZX2967_WDT_REFRESH_REG);
  56. /*
  57. * Bit 4-5, 1 and 2: refresh config info
  58. * Bit 2-3, 1 and 2: refresh counter
  59. * Bit 0-1, 1 and 2: refresh int-value
  60. * we shift each group value between 1 and 2 to refresh all data.
  61. */
  62. val ^= ZX2967_WDT_REFRESH_MASK;
  63. zx2967_wdt_writel(wdt, ZX2967_WDT_REFRESH_REG,
  64. val & ZX2967_WDT_VAL_MASK);
  65. }
  66. static int
  67. zx2967_wdt_set_timeout(struct watchdog_device *wdd, unsigned int timeout)
  68. {
  69. struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
  70. unsigned int divisor = ZX2967_WDT_DIV_DEFAULT;
  71. u32 count;
  72. count = timeout * ZX2967_WDT_CLK_FREQ;
  73. if (count > divisor * ZX2967_WDT_MAX_COUNT)
  74. divisor = DIV_ROUND_UP(count, ZX2967_WDT_MAX_COUNT);
  75. count = DIV_ROUND_UP(count, divisor);
  76. zx2967_wdt_writel(wdt, ZX2967_WDT_CFG_REG,
  77. ZX2967_WDT_CFG_DIV(divisor) & ZX2967_WDT_VAL_MASK);
  78. zx2967_wdt_writel(wdt, ZX2967_WDT_LOAD_REG,
  79. count & ZX2967_WDT_VAL_MASK);
  80. zx2967_wdt_refresh(wdt);
  81. wdd->timeout = (count * divisor) / ZX2967_WDT_CLK_FREQ;
  82. return 0;
  83. }
  84. static void __zx2967_wdt_start(struct zx2967_wdt *wdt)
  85. {
  86. u32 val;
  87. val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG);
  88. val |= ZX2967_WDT_START_EN;
  89. zx2967_wdt_writel(wdt, ZX2967_WDT_START_REG,
  90. val & ZX2967_WDT_VAL_MASK);
  91. }
  92. static void __zx2967_wdt_stop(struct zx2967_wdt *wdt)
  93. {
  94. u32 val;
  95. val = zx2967_wdt_readl(wdt, ZX2967_WDT_START_REG);
  96. val &= ~ZX2967_WDT_START_EN;
  97. zx2967_wdt_writel(wdt, ZX2967_WDT_START_REG,
  98. val & ZX2967_WDT_VAL_MASK);
  99. }
  100. static int zx2967_wdt_start(struct watchdog_device *wdd)
  101. {
  102. struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
  103. zx2967_wdt_set_timeout(wdd, wdd->timeout);
  104. __zx2967_wdt_start(wdt);
  105. return 0;
  106. }
  107. static int zx2967_wdt_stop(struct watchdog_device *wdd)
  108. {
  109. struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
  110. __zx2967_wdt_stop(wdt);
  111. return 0;
  112. }
  113. static int zx2967_wdt_keepalive(struct watchdog_device *wdd)
  114. {
  115. struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
  116. zx2967_wdt_refresh(wdt);
  117. return 0;
  118. }
  119. #define ZX2967_WDT_OPTIONS \
  120. (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
  121. static const struct watchdog_info zx2967_wdt_ident = {
  122. .options = ZX2967_WDT_OPTIONS,
  123. .identity = "zx2967 watchdog",
  124. };
  125. static const struct watchdog_ops zx2967_wdt_ops = {
  126. .owner = THIS_MODULE,
  127. .start = zx2967_wdt_start,
  128. .stop = zx2967_wdt_stop,
  129. .ping = zx2967_wdt_keepalive,
  130. .set_timeout = zx2967_wdt_set_timeout,
  131. };
  132. static void zx2967_wdt_reset_sysctrl(struct device *dev)
  133. {
  134. int ret;
  135. void __iomem *regmap;
  136. unsigned int offset, mask, config;
  137. struct of_phandle_args out_args;
  138. ret = of_parse_phandle_with_fixed_args(dev->of_node,
  139. "zte,wdt-reset-sysctrl", 3, 0, &out_args);
  140. if (ret)
  141. return;
  142. offset = out_args.args[0];
  143. config = out_args.args[1];
  144. mask = out_args.args[2];
  145. regmap = syscon_node_to_regmap(out_args.np);
  146. if (IS_ERR(regmap)) {
  147. of_node_put(out_args.np);
  148. return;
  149. }
  150. regmap_update_bits(regmap, offset, mask, config);
  151. of_node_put(out_args.np);
  152. }
  153. static void zx2967_clk_disable_unprepare(void *data)
  154. {
  155. clk_disable_unprepare(data);
  156. }
  157. static int zx2967_wdt_probe(struct platform_device *pdev)
  158. {
  159. struct device *dev = &pdev->dev;
  160. struct zx2967_wdt *wdt;
  161. int ret;
  162. struct reset_control *rstc;
  163. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  164. if (!wdt)
  165. return -ENOMEM;
  166. platform_set_drvdata(pdev, wdt);
  167. wdt->wdt_device.info = &zx2967_wdt_ident;
  168. wdt->wdt_device.ops = &zx2967_wdt_ops;
  169. wdt->wdt_device.timeout = ZX2967_WDT_DEFAULT_TIMEOUT;
  170. wdt->wdt_device.max_timeout = ZX2967_WDT_MAX_TIMEOUT;
  171. wdt->wdt_device.min_timeout = ZX2967_WDT_MIN_TIMEOUT;
  172. wdt->wdt_device.parent = dev;
  173. wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
  174. if (IS_ERR(wdt->reg_base))
  175. return PTR_ERR(wdt->reg_base);
  176. zx2967_wdt_reset_sysctrl(dev);
  177. wdt->clock = devm_clk_get(dev, NULL);
  178. if (IS_ERR(wdt->clock)) {
  179. dev_err(dev, "failed to find watchdog clock source\n");
  180. return PTR_ERR(wdt->clock);
  181. }
  182. ret = clk_prepare_enable(wdt->clock);
  183. if (ret < 0) {
  184. dev_err(dev, "failed to enable clock\n");
  185. return ret;
  186. }
  187. ret = devm_add_action_or_reset(dev, zx2967_clk_disable_unprepare,
  188. wdt->clock);
  189. if (ret)
  190. return ret;
  191. clk_set_rate(wdt->clock, ZX2967_WDT_CLK_FREQ);
  192. rstc = devm_reset_control_get_exclusive(dev, NULL);
  193. if (IS_ERR(rstc)) {
  194. dev_err(dev, "failed to get rstc");
  195. return PTR_ERR(rstc);
  196. }
  197. reset_control_assert(rstc);
  198. reset_control_deassert(rstc);
  199. watchdog_set_drvdata(&wdt->wdt_device, wdt);
  200. watchdog_init_timeout(&wdt->wdt_device,
  201. ZX2967_WDT_DEFAULT_TIMEOUT, dev);
  202. watchdog_set_nowayout(&wdt->wdt_device, WATCHDOG_NOWAYOUT);
  203. ret = devm_watchdog_register_device(dev, &wdt->wdt_device);
  204. if (ret)
  205. return ret;
  206. dev_info(dev, "watchdog enabled (timeout=%d sec, nowayout=%d)",
  207. wdt->wdt_device.timeout, WATCHDOG_NOWAYOUT);
  208. return 0;
  209. }
  210. static const struct of_device_id zx2967_wdt_match[] = {
  211. { .compatible = "zte,zx296718-wdt", },
  212. {}
  213. };
  214. MODULE_DEVICE_TABLE(of, zx2967_wdt_match);
  215. static struct platform_driver zx2967_wdt_driver = {
  216. .probe = zx2967_wdt_probe,
  217. .driver = {
  218. .name = "zx2967-wdt",
  219. .of_match_table = of_match_ptr(zx2967_wdt_match),
  220. },
  221. };
  222. module_platform_driver(zx2967_wdt_driver);
  223. MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
  224. MODULE_DESCRIPTION("ZTE zx2967 Watchdog Device Driver");
  225. MODULE_LICENSE("GPL v2");