sprd_wdt.c 8.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Spreadtrum watchdog driver
  4. * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
  5. */
  6. #include <linux/bitops.h>
  7. #include <linux/clk.h>
  8. #include <linux/device.h>
  9. #include <linux/err.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/watchdog.h>
  18. #define SPRD_WDT_LOAD_LOW 0x0
  19. #define SPRD_WDT_LOAD_HIGH 0x4
  20. #define SPRD_WDT_CTRL 0x8
  21. #define SPRD_WDT_INT_CLR 0xc
  22. #define SPRD_WDT_INT_RAW 0x10
  23. #define SPRD_WDT_INT_MSK 0x14
  24. #define SPRD_WDT_CNT_LOW 0x18
  25. #define SPRD_WDT_CNT_HIGH 0x1c
  26. #define SPRD_WDT_LOCK 0x20
  27. #define SPRD_WDT_IRQ_LOAD_LOW 0x2c
  28. #define SPRD_WDT_IRQ_LOAD_HIGH 0x30
  29. /* WDT_CTRL */
  30. #define SPRD_WDT_INT_EN_BIT BIT(0)
  31. #define SPRD_WDT_CNT_EN_BIT BIT(1)
  32. #define SPRD_WDT_NEW_VER_EN BIT(2)
  33. #define SPRD_WDT_RST_EN_BIT BIT(3)
  34. /* WDT_INT_CLR */
  35. #define SPRD_WDT_INT_CLEAR_BIT BIT(0)
  36. #define SPRD_WDT_RST_CLEAR_BIT BIT(3)
  37. /* WDT_INT_RAW */
  38. #define SPRD_WDT_INT_RAW_BIT BIT(0)
  39. #define SPRD_WDT_RST_RAW_BIT BIT(3)
  40. #define SPRD_WDT_LD_BUSY_BIT BIT(4)
  41. /* 1s equal to 32768 counter steps */
  42. #define SPRD_WDT_CNT_STEP 32768
  43. #define SPRD_WDT_UNLOCK_KEY 0xe551
  44. #define SPRD_WDT_MIN_TIMEOUT 3
  45. #define SPRD_WDT_MAX_TIMEOUT 60
  46. #define SPRD_WDT_CNT_HIGH_SHIFT 16
  47. #define SPRD_WDT_LOW_VALUE_MASK GENMASK(15, 0)
  48. #define SPRD_WDT_LOAD_TIMEOUT 1000
  49. struct sprd_wdt {
  50. void __iomem *base;
  51. struct watchdog_device wdd;
  52. struct clk *enable;
  53. struct clk *rtc_enable;
  54. int irq;
  55. };
  56. static inline struct sprd_wdt *to_sprd_wdt(struct watchdog_device *wdd)
  57. {
  58. return container_of(wdd, struct sprd_wdt, wdd);
  59. }
  60. static inline void sprd_wdt_lock(void __iomem *addr)
  61. {
  62. writel_relaxed(0x0, addr + SPRD_WDT_LOCK);
  63. }
  64. static inline void sprd_wdt_unlock(void __iomem *addr)
  65. {
  66. writel_relaxed(SPRD_WDT_UNLOCK_KEY, addr + SPRD_WDT_LOCK);
  67. }
  68. static irqreturn_t sprd_wdt_isr(int irq, void *dev_id)
  69. {
  70. struct sprd_wdt *wdt = (struct sprd_wdt *)dev_id;
  71. sprd_wdt_unlock(wdt->base);
  72. writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR);
  73. sprd_wdt_lock(wdt->base);
  74. watchdog_notify_pretimeout(&wdt->wdd);
  75. return IRQ_HANDLED;
  76. }
  77. static u32 sprd_wdt_get_cnt_value(struct sprd_wdt *wdt)
  78. {
  79. u32 val;
  80. val = readl_relaxed(wdt->base + SPRD_WDT_CNT_HIGH) <<
  81. SPRD_WDT_CNT_HIGH_SHIFT;
  82. val |= readl_relaxed(wdt->base + SPRD_WDT_CNT_LOW) &
  83. SPRD_WDT_LOW_VALUE_MASK;
  84. return val;
  85. }
  86. static int sprd_wdt_load_value(struct sprd_wdt *wdt, u32 timeout,
  87. u32 pretimeout)
  88. {
  89. u32 val, delay_cnt = 0;
  90. u32 tmr_step = timeout * SPRD_WDT_CNT_STEP;
  91. u32 prtmr_step = pretimeout * SPRD_WDT_CNT_STEP;
  92. /*
  93. * Waiting the load value operation done,
  94. * it needs two or three RTC clock cycles.
  95. */
  96. do {
  97. val = readl_relaxed(wdt->base + SPRD_WDT_INT_RAW);
  98. if (!(val & SPRD_WDT_LD_BUSY_BIT))
  99. break;
  100. cpu_relax();
  101. } while (delay_cnt++ < SPRD_WDT_LOAD_TIMEOUT);
  102. if (delay_cnt >= SPRD_WDT_LOAD_TIMEOUT)
  103. return -EBUSY;
  104. sprd_wdt_unlock(wdt->base);
  105. writel_relaxed((tmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
  106. SPRD_WDT_LOW_VALUE_MASK, wdt->base + SPRD_WDT_LOAD_HIGH);
  107. writel_relaxed((tmr_step & SPRD_WDT_LOW_VALUE_MASK),
  108. wdt->base + SPRD_WDT_LOAD_LOW);
  109. writel_relaxed((prtmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) &
  110. SPRD_WDT_LOW_VALUE_MASK,
  111. wdt->base + SPRD_WDT_IRQ_LOAD_HIGH);
  112. writel_relaxed(prtmr_step & SPRD_WDT_LOW_VALUE_MASK,
  113. wdt->base + SPRD_WDT_IRQ_LOAD_LOW);
  114. sprd_wdt_lock(wdt->base);
  115. return 0;
  116. }
  117. static int sprd_wdt_enable(struct sprd_wdt *wdt)
  118. {
  119. u32 val;
  120. int ret;
  121. ret = clk_prepare_enable(wdt->enable);
  122. if (ret)
  123. return ret;
  124. ret = clk_prepare_enable(wdt->rtc_enable);
  125. if (ret) {
  126. clk_disable_unprepare(wdt->enable);
  127. return ret;
  128. }
  129. sprd_wdt_unlock(wdt->base);
  130. val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
  131. val |= SPRD_WDT_NEW_VER_EN;
  132. writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
  133. sprd_wdt_lock(wdt->base);
  134. return 0;
  135. }
  136. static void sprd_wdt_disable(void *_data)
  137. {
  138. struct sprd_wdt *wdt = _data;
  139. sprd_wdt_unlock(wdt->base);
  140. writel_relaxed(0x0, wdt->base + SPRD_WDT_CTRL);
  141. sprd_wdt_lock(wdt->base);
  142. clk_disable_unprepare(wdt->rtc_enable);
  143. clk_disable_unprepare(wdt->enable);
  144. }
  145. static int sprd_wdt_start(struct watchdog_device *wdd)
  146. {
  147. struct sprd_wdt *wdt = to_sprd_wdt(wdd);
  148. u32 val;
  149. int ret;
  150. ret = sprd_wdt_load_value(wdt, wdd->timeout, wdd->pretimeout);
  151. if (ret)
  152. return ret;
  153. sprd_wdt_unlock(wdt->base);
  154. val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
  155. val |= SPRD_WDT_CNT_EN_BIT | SPRD_WDT_INT_EN_BIT | SPRD_WDT_RST_EN_BIT;
  156. writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
  157. sprd_wdt_lock(wdt->base);
  158. set_bit(WDOG_HW_RUNNING, &wdd->status);
  159. return 0;
  160. }
  161. static int sprd_wdt_stop(struct watchdog_device *wdd)
  162. {
  163. struct sprd_wdt *wdt = to_sprd_wdt(wdd);
  164. u32 val;
  165. sprd_wdt_unlock(wdt->base);
  166. val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
  167. val &= ~(SPRD_WDT_CNT_EN_BIT | SPRD_WDT_RST_EN_BIT |
  168. SPRD_WDT_INT_EN_BIT);
  169. writel_relaxed(val, wdt->base + SPRD_WDT_CTRL);
  170. sprd_wdt_lock(wdt->base);
  171. return 0;
  172. }
  173. static int sprd_wdt_set_timeout(struct watchdog_device *wdd,
  174. u32 timeout)
  175. {
  176. struct sprd_wdt *wdt = to_sprd_wdt(wdd);
  177. if (timeout == wdd->timeout)
  178. return 0;
  179. wdd->timeout = timeout;
  180. return sprd_wdt_load_value(wdt, timeout, wdd->pretimeout);
  181. }
  182. static int sprd_wdt_set_pretimeout(struct watchdog_device *wdd,
  183. u32 new_pretimeout)
  184. {
  185. struct sprd_wdt *wdt = to_sprd_wdt(wdd);
  186. if (new_pretimeout < wdd->min_timeout)
  187. return -EINVAL;
  188. wdd->pretimeout = new_pretimeout;
  189. return sprd_wdt_load_value(wdt, wdd->timeout, new_pretimeout);
  190. }
  191. static u32 sprd_wdt_get_timeleft(struct watchdog_device *wdd)
  192. {
  193. struct sprd_wdt *wdt = to_sprd_wdt(wdd);
  194. u32 val;
  195. val = sprd_wdt_get_cnt_value(wdt);
  196. return val / SPRD_WDT_CNT_STEP;
  197. }
  198. static const struct watchdog_ops sprd_wdt_ops = {
  199. .owner = THIS_MODULE,
  200. .start = sprd_wdt_start,
  201. .stop = sprd_wdt_stop,
  202. .set_timeout = sprd_wdt_set_timeout,
  203. .set_pretimeout = sprd_wdt_set_pretimeout,
  204. .get_timeleft = sprd_wdt_get_timeleft,
  205. };
  206. static const struct watchdog_info sprd_wdt_info = {
  207. .options = WDIOF_SETTIMEOUT |
  208. WDIOF_PRETIMEOUT |
  209. WDIOF_MAGICCLOSE |
  210. WDIOF_KEEPALIVEPING,
  211. .identity = "Spreadtrum Watchdog Timer",
  212. };
  213. static int sprd_wdt_probe(struct platform_device *pdev)
  214. {
  215. struct device *dev = &pdev->dev;
  216. struct sprd_wdt *wdt;
  217. int ret;
  218. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  219. if (!wdt)
  220. return -ENOMEM;
  221. wdt->base = devm_platform_ioremap_resource(pdev, 0);
  222. if (IS_ERR(wdt->base))
  223. return PTR_ERR(wdt->base);
  224. wdt->enable = devm_clk_get(dev, "enable");
  225. if (IS_ERR(wdt->enable)) {
  226. dev_err(dev, "can't get the enable clock\n");
  227. return PTR_ERR(wdt->enable);
  228. }
  229. wdt->rtc_enable = devm_clk_get(dev, "rtc_enable");
  230. if (IS_ERR(wdt->rtc_enable)) {
  231. dev_err(dev, "can't get the rtc enable clock\n");
  232. return PTR_ERR(wdt->rtc_enable);
  233. }
  234. wdt->irq = platform_get_irq(pdev, 0);
  235. if (wdt->irq < 0)
  236. return wdt->irq;
  237. ret = devm_request_irq(dev, wdt->irq, sprd_wdt_isr, IRQF_NO_SUSPEND,
  238. "sprd-wdt", (void *)wdt);
  239. if (ret) {
  240. dev_err(dev, "failed to register irq\n");
  241. return ret;
  242. }
  243. wdt->wdd.info = &sprd_wdt_info;
  244. wdt->wdd.ops = &sprd_wdt_ops;
  245. wdt->wdd.parent = dev;
  246. wdt->wdd.min_timeout = SPRD_WDT_MIN_TIMEOUT;
  247. wdt->wdd.max_timeout = SPRD_WDT_MAX_TIMEOUT;
  248. wdt->wdd.timeout = SPRD_WDT_MAX_TIMEOUT;
  249. ret = sprd_wdt_enable(wdt);
  250. if (ret) {
  251. dev_err(dev, "failed to enable wdt\n");
  252. return ret;
  253. }
  254. ret = devm_add_action_or_reset(dev, sprd_wdt_disable, wdt);
  255. if (ret) {
  256. dev_err(dev, "Failed to add wdt disable action\n");
  257. return ret;
  258. }
  259. watchdog_set_nowayout(&wdt->wdd, WATCHDOG_NOWAYOUT);
  260. watchdog_init_timeout(&wdt->wdd, 0, dev);
  261. ret = devm_watchdog_register_device(dev, &wdt->wdd);
  262. if (ret) {
  263. sprd_wdt_disable(wdt);
  264. return ret;
  265. }
  266. platform_set_drvdata(pdev, wdt);
  267. return 0;
  268. }
  269. static int __maybe_unused sprd_wdt_pm_suspend(struct device *dev)
  270. {
  271. struct sprd_wdt *wdt = dev_get_drvdata(dev);
  272. if (watchdog_active(&wdt->wdd))
  273. sprd_wdt_stop(&wdt->wdd);
  274. sprd_wdt_disable(wdt);
  275. return 0;
  276. }
  277. static int __maybe_unused sprd_wdt_pm_resume(struct device *dev)
  278. {
  279. struct sprd_wdt *wdt = dev_get_drvdata(dev);
  280. int ret;
  281. ret = sprd_wdt_enable(wdt);
  282. if (ret)
  283. return ret;
  284. if (watchdog_active(&wdt->wdd))
  285. ret = sprd_wdt_start(&wdt->wdd);
  286. return ret;
  287. }
  288. static const struct dev_pm_ops sprd_wdt_pm_ops = {
  289. SET_SYSTEM_SLEEP_PM_OPS(sprd_wdt_pm_suspend,
  290. sprd_wdt_pm_resume)
  291. };
  292. static const struct of_device_id sprd_wdt_match_table[] = {
  293. { .compatible = "sprd,sp9860-wdt", },
  294. {},
  295. };
  296. MODULE_DEVICE_TABLE(of, sprd_wdt_match_table);
  297. static struct platform_driver sprd_watchdog_driver = {
  298. .probe = sprd_wdt_probe,
  299. .driver = {
  300. .name = "sprd-wdt",
  301. .of_match_table = sprd_wdt_match_table,
  302. .pm = &sprd_wdt_pm_ops,
  303. },
  304. };
  305. module_platform_driver(sprd_watchdog_driver);
  306. MODULE_AUTHOR("Eric Long <eric.long@spreadtrum.com>");
  307. MODULE_DESCRIPTION("Spreadtrum Watchdog Timer Controller Driver");
  308. MODULE_LICENSE("GPL v2");