sp5100_tco.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * sp5100_tco: TCO timer driver for sp5100 chipsets.
  4. *
  5. * (c) Copyright 2009 Google Inc., All Rights Reserved.
  6. *
  7. * TCO timer driver for sp5100 chipsets
  8. */
  9. #include <linux/bitops.h>
  10. /*
  11. * Some address definitions for the Watchdog
  12. */
  13. #define SP5100_WDT_MEM_MAP_SIZE 0x08
  14. #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
  15. #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
  16. #define SP5100_WDT_START_STOP_BIT BIT(0)
  17. #define SP5100_WDT_FIRED BIT(1)
  18. #define SP5100_WDT_ACTION_RESET BIT(2)
  19. #define SP5100_WDT_DISABLED BIT(3)
  20. #define SP5100_WDT_TRIGGER_BIT BIT(7)
  21. #define SP5100_PM_IOPORTS_SIZE 0x02
  22. /*
  23. * These two IO registers are hardcoded and there doesn't seem to be a way to
  24. * read them from a register.
  25. */
  26. /* For SP5100/SB7x0/SB8x0 chipset */
  27. #define SP5100_IO_PM_INDEX_REG 0xCD6
  28. #define SP5100_IO_PM_DATA_REG 0xCD7
  29. /* For SP5100/SB7x0 chipset */
  30. #define SP5100_SB_RESOURCE_MMIO_BASE 0x9C
  31. #define SP5100_PM_WATCHDOG_CONTROL 0x69
  32. #define SP5100_PM_WATCHDOG_BASE 0x6C
  33. #define SP5100_PCI_WATCHDOG_MISC_REG 0x41
  34. #define SP5100_PCI_WATCHDOG_DECODE_EN BIT(3)
  35. #define SP5100_PM_WATCHDOG_DISABLE ((u8)BIT(0))
  36. #define SP5100_PM_WATCHDOG_SECOND_RES GENMASK(2, 1)
  37. #define SP5100_DEVNAME "SP5100 TCO"
  38. /* For SB8x0(or later) chipset */
  39. #define SB800_PM_ACPI_MMIO_EN 0x24
  40. #define SB800_PM_WATCHDOG_CONTROL 0x48
  41. #define SB800_PM_WATCHDOG_BASE 0x48
  42. #define SB800_PM_WATCHDOG_CONFIG 0x4C
  43. #define SB800_PCI_WATCHDOG_DECODE_EN BIT(0)
  44. #define SB800_PM_WATCHDOG_DISABLE ((u8)BIT(1))
  45. #define SB800_PM_WATCHDOG_SECOND_RES GENMASK(1, 0)
  46. #define SB800_ACPI_MMIO_DECODE_EN BIT(0)
  47. #define SB800_ACPI_MMIO_SEL BIT(1)
  48. #define SB800_PM_WDT_MMIO_OFFSET 0xB00
  49. #define SB800_DEVNAME "SB800 TCO"
  50. /* For recent chips with embedded FCH (rev 40+) */
  51. #define EFCH_PM_DECODEEN 0x00
  52. #define EFCH_PM_DECODEEN_WDT_TMREN BIT(7)
  53. #define EFCH_PM_DECODEEN3 0x03
  54. #define EFCH_PM_DECODEEN_SECOND_RES GENMASK(1, 0)
  55. #define EFCH_PM_WATCHDOG_DISABLE ((u8)GENMASK(3, 2))
  56. /* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */
  57. #define EFCH_PM_WDT_ADDR 0xfeb00000
  58. #define EFCH_PM_ISACONTROL 0x04
  59. #define EFCH_PM_ISACONTROL_MMIOEN BIT(1)
  60. #define EFCH_PM_ACPI_MMIO_ADDR 0xfed80000
  61. #define EFCH_PM_ACPI_MMIO_WDT_OFFSET 0x00000b00