sbsa_gwdt.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SBSA(Server Base System Architecture) Generic Watchdog driver
  4. *
  5. * Copyright (c) 2015, Linaro Ltd.
  6. * Author: Fu Wei <fu.wei@linaro.org>
  7. * Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
  8. * Al Stone <al.stone@linaro.org>
  9. * Timur Tabi <timur@codeaurora.org>
  10. *
  11. * ARM SBSA Generic Watchdog has two stage timeouts:
  12. * the first signal (WS0) is for alerting the system by interrupt,
  13. * the second one (WS1) is a real hardware reset.
  14. * More details about the hardware specification of this device:
  15. * ARM DEN0029B - Server Base System Architecture (SBSA)
  16. *
  17. * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
  18. * or a two stages watchdog, it's set up by the module parameter "action".
  19. * In the single stage mode, when the timeout is reached, your system
  20. * will be reset by WS1. The first signal (WS0) is ignored.
  21. * In the two stages mode, when the timeout is reached, the first signal (WS0)
  22. * will trigger panic. If the system is getting into trouble and cannot be reset
  23. * by panic or restart properly by the kdump kernel(if supported), then the
  24. * second stage (as long as the first stage) will be reached, system will be
  25. * reset by WS1. This function can help administrator to backup the system
  26. * context info by panic console output or kdump.
  27. *
  28. * SBSA GWDT:
  29. * if action is 1 (the two stages mode):
  30. * |--------WOR-------WS0--------WOR-------WS1
  31. * |----timeout-----(panic)----timeout-----reset
  32. *
  33. * if action is 0 (the single stage mode):
  34. * |------WOR-----WS0(ignored)-----WOR------WS1
  35. * |--------------timeout-------------------reset
  36. *
  37. * Note: Since this watchdog timer has two stages, and each stage is determined
  38. * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
  39. * stages mode, the timeout is WOR. The maximum timeout in the two stages mode
  40. * is half of that in the single stage mode.
  41. */
  42. #include <linux/io.h>
  43. #include <linux/io-64-nonatomic-lo-hi.h>
  44. #include <linux/interrupt.h>
  45. #include <linux/module.h>
  46. #include <linux/moduleparam.h>
  47. #include <linux/of.h>
  48. #include <linux/of_device.h>
  49. #include <linux/platform_device.h>
  50. #include <linux/uaccess.h>
  51. #include <linux/watchdog.h>
  52. #include <asm/arch_timer.h>
  53. #define DRV_NAME "sbsa-gwdt"
  54. #define WATCHDOG_NAME "SBSA Generic Watchdog"
  55. /* SBSA Generic Watchdog register definitions */
  56. /* refresh frame */
  57. #define SBSA_GWDT_WRR 0x000
  58. /* control frame */
  59. #define SBSA_GWDT_WCS 0x000
  60. #define SBSA_GWDT_WOR 0x008
  61. #define SBSA_GWDT_WCV 0x010
  62. /* refresh/control frame */
  63. #define SBSA_GWDT_W_IIDR 0xfcc
  64. #define SBSA_GWDT_IDR 0xfd0
  65. /* Watchdog Control and Status Register */
  66. #define SBSA_GWDT_WCS_EN BIT(0)
  67. #define SBSA_GWDT_WCS_WS0 BIT(1)
  68. #define SBSA_GWDT_WCS_WS1 BIT(2)
  69. /**
  70. * struct sbsa_gwdt - Internal representation of the SBSA GWDT
  71. * @wdd: kernel watchdog_device structure
  72. * @clk: store the System Counter clock frequency, in Hz.
  73. * @refresh_base: Virtual address of the watchdog refresh frame
  74. * @control_base: Virtual address of the watchdog control frame
  75. */
  76. struct sbsa_gwdt {
  77. struct watchdog_device wdd;
  78. u32 clk;
  79. void __iomem *refresh_base;
  80. void __iomem *control_base;
  81. };
  82. #define DEFAULT_TIMEOUT 10 /* seconds */
  83. static unsigned int timeout;
  84. module_param(timeout, uint, 0);
  85. MODULE_PARM_DESC(timeout,
  86. "Watchdog timeout in seconds. (>=0, default="
  87. __MODULE_STRING(DEFAULT_TIMEOUT) ")");
  88. /*
  89. * action refers to action taken when watchdog gets WS0
  90. * 0 = skip
  91. * 1 = panic
  92. * defaults to skip (0)
  93. */
  94. static int action;
  95. module_param(action, int, 0);
  96. MODULE_PARM_DESC(action, "after watchdog gets WS0 interrupt, do: "
  97. "0 = skip(*) 1 = panic");
  98. static bool nowayout = WATCHDOG_NOWAYOUT;
  99. module_param(nowayout, bool, S_IRUGO);
  100. MODULE_PARM_DESC(nowayout,
  101. "Watchdog cannot be stopped once started (default="
  102. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  103. /*
  104. * watchdog operation functions
  105. */
  106. static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd,
  107. unsigned int timeout)
  108. {
  109. struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
  110. wdd->timeout = timeout;
  111. if (action)
  112. writel(gwdt->clk * timeout,
  113. gwdt->control_base + SBSA_GWDT_WOR);
  114. else
  115. /*
  116. * In the single stage mode, The first signal (WS0) is ignored,
  117. * the timeout is (WOR * 2), so the WOR should be configured
  118. * to half value of timeout.
  119. */
  120. writel(gwdt->clk / 2 * timeout,
  121. gwdt->control_base + SBSA_GWDT_WOR);
  122. return 0;
  123. }
  124. static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
  125. {
  126. struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
  127. u64 timeleft = 0;
  128. /*
  129. * In the single stage mode, if WS0 is deasserted
  130. * (watchdog is in the first stage),
  131. * timeleft = WOR + (WCV - system counter)
  132. */
  133. if (!action &&
  134. !(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0))
  135. timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR);
  136. timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) -
  137. arch_timer_read_counter();
  138. do_div(timeleft, gwdt->clk);
  139. return timeleft;
  140. }
  141. static int sbsa_gwdt_keepalive(struct watchdog_device *wdd)
  142. {
  143. struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
  144. /*
  145. * Writing WRR for an explicit watchdog refresh.
  146. * You can write anyting (like 0).
  147. */
  148. writel(0, gwdt->refresh_base + SBSA_GWDT_WRR);
  149. return 0;
  150. }
  151. static int sbsa_gwdt_start(struct watchdog_device *wdd)
  152. {
  153. struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
  154. /* writing WCS will cause an explicit watchdog refresh */
  155. writel(SBSA_GWDT_WCS_EN, gwdt->control_base + SBSA_GWDT_WCS);
  156. return 0;
  157. }
  158. static int sbsa_gwdt_stop(struct watchdog_device *wdd)
  159. {
  160. struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd);
  161. /* Simply write 0 to WCS to clean WCS_EN bit */
  162. writel(0, gwdt->control_base + SBSA_GWDT_WCS);
  163. return 0;
  164. }
  165. static irqreturn_t sbsa_gwdt_interrupt(int irq, void *dev_id)
  166. {
  167. panic(WATCHDOG_NAME " timeout");
  168. return IRQ_HANDLED;
  169. }
  170. static const struct watchdog_info sbsa_gwdt_info = {
  171. .identity = WATCHDOG_NAME,
  172. .options = WDIOF_SETTIMEOUT |
  173. WDIOF_KEEPALIVEPING |
  174. WDIOF_MAGICCLOSE |
  175. WDIOF_CARDRESET,
  176. };
  177. static const struct watchdog_ops sbsa_gwdt_ops = {
  178. .owner = THIS_MODULE,
  179. .start = sbsa_gwdt_start,
  180. .stop = sbsa_gwdt_stop,
  181. .ping = sbsa_gwdt_keepalive,
  182. .set_timeout = sbsa_gwdt_set_timeout,
  183. .get_timeleft = sbsa_gwdt_get_timeleft,
  184. };
  185. static int sbsa_gwdt_probe(struct platform_device *pdev)
  186. {
  187. void __iomem *rf_base, *cf_base;
  188. struct device *dev = &pdev->dev;
  189. struct watchdog_device *wdd;
  190. struct sbsa_gwdt *gwdt;
  191. int ret, irq;
  192. u32 status;
  193. gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
  194. if (!gwdt)
  195. return -ENOMEM;
  196. platform_set_drvdata(pdev, gwdt);
  197. cf_base = devm_platform_ioremap_resource(pdev, 0);
  198. if (IS_ERR(cf_base))
  199. return PTR_ERR(cf_base);
  200. rf_base = devm_platform_ioremap_resource(pdev, 1);
  201. if (IS_ERR(rf_base))
  202. return PTR_ERR(rf_base);
  203. /*
  204. * Get the frequency of system counter from the cp15 interface of ARM
  205. * Generic timer. We don't need to check it, because if it returns "0",
  206. * system would panic in very early stage.
  207. */
  208. gwdt->clk = arch_timer_get_cntfrq();
  209. gwdt->refresh_base = rf_base;
  210. gwdt->control_base = cf_base;
  211. wdd = &gwdt->wdd;
  212. wdd->parent = dev;
  213. wdd->info = &sbsa_gwdt_info;
  214. wdd->ops = &sbsa_gwdt_ops;
  215. wdd->min_timeout = 1;
  216. wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000;
  217. wdd->timeout = DEFAULT_TIMEOUT;
  218. watchdog_set_drvdata(wdd, gwdt);
  219. watchdog_set_nowayout(wdd, nowayout);
  220. status = readl(cf_base + SBSA_GWDT_WCS);
  221. if (status & SBSA_GWDT_WCS_WS1) {
  222. dev_warn(dev, "System reset by WDT.\n");
  223. wdd->bootstatus |= WDIOF_CARDRESET;
  224. }
  225. if (status & SBSA_GWDT_WCS_EN)
  226. set_bit(WDOG_HW_RUNNING, &wdd->status);
  227. if (action) {
  228. irq = platform_get_irq(pdev, 0);
  229. if (irq < 0) {
  230. action = 0;
  231. dev_warn(dev, "unable to get ws0 interrupt.\n");
  232. } else {
  233. /*
  234. * In case there is a pending ws0 interrupt, just ping
  235. * the watchdog before registering the interrupt routine
  236. */
  237. writel(0, rf_base + SBSA_GWDT_WRR);
  238. if (devm_request_irq(dev, irq, sbsa_gwdt_interrupt, 0,
  239. pdev->name, gwdt)) {
  240. action = 0;
  241. dev_warn(dev, "unable to request IRQ %d.\n",
  242. irq);
  243. }
  244. }
  245. if (!action)
  246. dev_warn(dev, "falling back to single stage mode.\n");
  247. }
  248. /*
  249. * In the single stage mode, The first signal (WS0) is ignored,
  250. * the timeout is (WOR * 2), so the maximum timeout should be doubled.
  251. */
  252. if (!action)
  253. wdd->max_hw_heartbeat_ms *= 2;
  254. watchdog_init_timeout(wdd, timeout, dev);
  255. /*
  256. * Update timeout to WOR.
  257. * Because of the explicit watchdog refresh mechanism,
  258. * it's also a ping, if watchdog is enabled.
  259. */
  260. sbsa_gwdt_set_timeout(wdd, wdd->timeout);
  261. watchdog_stop_on_reboot(wdd);
  262. ret = devm_watchdog_register_device(dev, wdd);
  263. if (ret)
  264. return ret;
  265. dev_info(dev, "Initialized with %ds timeout @ %u Hz, action=%d.%s\n",
  266. wdd->timeout, gwdt->clk, action,
  267. status & SBSA_GWDT_WCS_EN ? " [enabled]" : "");
  268. return 0;
  269. }
  270. /* Disable watchdog if it is active during suspend */
  271. static int __maybe_unused sbsa_gwdt_suspend(struct device *dev)
  272. {
  273. struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
  274. if (watchdog_active(&gwdt->wdd))
  275. sbsa_gwdt_stop(&gwdt->wdd);
  276. return 0;
  277. }
  278. /* Enable watchdog if necessary */
  279. static int __maybe_unused sbsa_gwdt_resume(struct device *dev)
  280. {
  281. struct sbsa_gwdt *gwdt = dev_get_drvdata(dev);
  282. if (watchdog_active(&gwdt->wdd))
  283. sbsa_gwdt_start(&gwdt->wdd);
  284. return 0;
  285. }
  286. static const struct dev_pm_ops sbsa_gwdt_pm_ops = {
  287. SET_SYSTEM_SLEEP_PM_OPS(sbsa_gwdt_suspend, sbsa_gwdt_resume)
  288. };
  289. static const struct of_device_id sbsa_gwdt_of_match[] = {
  290. { .compatible = "arm,sbsa-gwdt", },
  291. {},
  292. };
  293. MODULE_DEVICE_TABLE(of, sbsa_gwdt_of_match);
  294. static const struct platform_device_id sbsa_gwdt_pdev_match[] = {
  295. { .name = DRV_NAME, },
  296. {},
  297. };
  298. MODULE_DEVICE_TABLE(platform, sbsa_gwdt_pdev_match);
  299. static struct platform_driver sbsa_gwdt_driver = {
  300. .driver = {
  301. .name = DRV_NAME,
  302. .pm = &sbsa_gwdt_pm_ops,
  303. .of_match_table = sbsa_gwdt_of_match,
  304. },
  305. .probe = sbsa_gwdt_probe,
  306. .id_table = sbsa_gwdt_pdev_match,
  307. };
  308. module_platform_driver(sbsa_gwdt_driver);
  309. MODULE_DESCRIPTION("SBSA Generic Watchdog Driver");
  310. MODULE_AUTHOR("Fu Wei <fu.wei@linaro.org>");
  311. MODULE_AUTHOR("Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>");
  312. MODULE_AUTHOR("Al Stone <al.stone@linaro.org>");
  313. MODULE_AUTHOR("Timur Tabi <timur@codeaurora.org>");
  314. MODULE_LICENSE("GPL v2");
  315. MODULE_ALIAS("platform:" DRV_NAME);