rt2880_wdt.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
  4. *
  5. * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
  6. * Copyright (C) 2013 John Crispin <john@phrozen.org>
  7. *
  8. * This driver was based on: drivers/watchdog/softdog.c
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/reset.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/watchdog.h>
  15. #include <linux/moduleparam.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/mod_devicetable.h>
  18. #include <asm/mach-ralink/ralink_regs.h>
  19. #define SYSC_RSTSTAT 0x38
  20. #define WDT_RST_CAUSE BIT(1)
  21. #define RALINK_WDT_TIMEOUT 30
  22. #define RALINK_WDT_PRESCALE 65536
  23. #define TIMER_REG_TMR1LOAD 0x00
  24. #define TIMER_REG_TMR1CTL 0x08
  25. #define TMRSTAT_TMR1RST BIT(5)
  26. #define TMR1CTL_ENABLE BIT(7)
  27. #define TMR1CTL_MODE_SHIFT 4
  28. #define TMR1CTL_MODE_MASK 0x3
  29. #define TMR1CTL_MODE_FREE_RUNNING 0x0
  30. #define TMR1CTL_MODE_PERIODIC 0x1
  31. #define TMR1CTL_MODE_TIMEOUT 0x2
  32. #define TMR1CTL_MODE_WDT 0x3
  33. #define TMR1CTL_PRESCALE_MASK 0xf
  34. #define TMR1CTL_PRESCALE_65536 0xf
  35. static struct clk *rt288x_wdt_clk;
  36. static unsigned long rt288x_wdt_freq;
  37. static void __iomem *rt288x_wdt_base;
  38. static struct reset_control *rt288x_wdt_reset;
  39. static bool nowayout = WATCHDOG_NOWAYOUT;
  40. module_param(nowayout, bool, 0);
  41. MODULE_PARM_DESC(nowayout,
  42. "Watchdog cannot be stopped once started (default="
  43. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  44. static inline void rt_wdt_w32(unsigned reg, u32 val)
  45. {
  46. iowrite32(val, rt288x_wdt_base + reg);
  47. }
  48. static inline u32 rt_wdt_r32(unsigned reg)
  49. {
  50. return ioread32(rt288x_wdt_base + reg);
  51. }
  52. static int rt288x_wdt_ping(struct watchdog_device *w)
  53. {
  54. rt_wdt_w32(TIMER_REG_TMR1LOAD, w->timeout * rt288x_wdt_freq);
  55. return 0;
  56. }
  57. static int rt288x_wdt_start(struct watchdog_device *w)
  58. {
  59. u32 t;
  60. t = rt_wdt_r32(TIMER_REG_TMR1CTL);
  61. t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT |
  62. TMR1CTL_PRESCALE_MASK);
  63. t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT |
  64. TMR1CTL_PRESCALE_65536);
  65. rt_wdt_w32(TIMER_REG_TMR1CTL, t);
  66. rt288x_wdt_ping(w);
  67. t = rt_wdt_r32(TIMER_REG_TMR1CTL);
  68. t |= TMR1CTL_ENABLE;
  69. rt_wdt_w32(TIMER_REG_TMR1CTL, t);
  70. return 0;
  71. }
  72. static int rt288x_wdt_stop(struct watchdog_device *w)
  73. {
  74. u32 t;
  75. rt288x_wdt_ping(w);
  76. t = rt_wdt_r32(TIMER_REG_TMR1CTL);
  77. t &= ~TMR1CTL_ENABLE;
  78. rt_wdt_w32(TIMER_REG_TMR1CTL, t);
  79. return 0;
  80. }
  81. static int rt288x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
  82. {
  83. w->timeout = t;
  84. rt288x_wdt_ping(w);
  85. return 0;
  86. }
  87. static int rt288x_wdt_bootcause(void)
  88. {
  89. if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
  90. return WDIOF_CARDRESET;
  91. return 0;
  92. }
  93. static const struct watchdog_info rt288x_wdt_info = {
  94. .identity = "Ralink Watchdog",
  95. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  96. };
  97. static const struct watchdog_ops rt288x_wdt_ops = {
  98. .owner = THIS_MODULE,
  99. .start = rt288x_wdt_start,
  100. .stop = rt288x_wdt_stop,
  101. .ping = rt288x_wdt_ping,
  102. .set_timeout = rt288x_wdt_set_timeout,
  103. };
  104. static struct watchdog_device rt288x_wdt_dev = {
  105. .info = &rt288x_wdt_info,
  106. .ops = &rt288x_wdt_ops,
  107. .min_timeout = 1,
  108. };
  109. static int rt288x_wdt_probe(struct platform_device *pdev)
  110. {
  111. struct device *dev = &pdev->dev;
  112. int ret;
  113. rt288x_wdt_base = devm_platform_ioremap_resource(pdev, 0);
  114. if (IS_ERR(rt288x_wdt_base))
  115. return PTR_ERR(rt288x_wdt_base);
  116. rt288x_wdt_clk = devm_clk_get(dev, NULL);
  117. if (IS_ERR(rt288x_wdt_clk))
  118. return PTR_ERR(rt288x_wdt_clk);
  119. rt288x_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
  120. if (!IS_ERR(rt288x_wdt_reset))
  121. reset_control_deassert(rt288x_wdt_reset);
  122. rt288x_wdt_freq = clk_get_rate(rt288x_wdt_clk) / RALINK_WDT_PRESCALE;
  123. rt288x_wdt_dev.bootstatus = rt288x_wdt_bootcause();
  124. rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
  125. rt288x_wdt_dev.parent = dev;
  126. watchdog_init_timeout(&rt288x_wdt_dev, rt288x_wdt_dev.max_timeout,
  127. dev);
  128. watchdog_set_nowayout(&rt288x_wdt_dev, nowayout);
  129. watchdog_stop_on_reboot(&rt288x_wdt_dev);
  130. ret = devm_watchdog_register_device(dev, &rt288x_wdt_dev);
  131. if (!ret)
  132. dev_info(dev, "Initialized\n");
  133. return 0;
  134. }
  135. static const struct of_device_id rt288x_wdt_match[] = {
  136. { .compatible = "ralink,rt2880-wdt" },
  137. {},
  138. };
  139. MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
  140. static struct platform_driver rt288x_wdt_driver = {
  141. .probe = rt288x_wdt_probe,
  142. .driver = {
  143. .name = KBUILD_MODNAME,
  144. .of_match_table = rt288x_wdt_match,
  145. },
  146. };
  147. module_platform_driver(rt288x_wdt_driver);
  148. MODULE_DESCRIPTION("MediaTek/Ralink RT288x/RT3xxx hardware watchdog driver");
  149. MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
  150. MODULE_LICENSE("GPL v2");