pic32-wdt.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * PIC32 watchdog driver
  4. *
  5. * Joshua Henderson <joshua.henderson@microchip.com>
  6. * Copyright (c) 2016, Microchip Technology Inc.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/device.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm.h>
  18. #include <linux/watchdog.h>
  19. #include <asm/mach-pic32/pic32.h>
  20. /* Watchdog Timer Registers */
  21. #define WDTCON_REG 0x00
  22. /* Watchdog Timer Control Register fields */
  23. #define WDTCON_WIN_EN BIT(0)
  24. #define WDTCON_RMCS_MASK 0x0003
  25. #define WDTCON_RMCS_SHIFT 0x0006
  26. #define WDTCON_RMPS_MASK 0x001F
  27. #define WDTCON_RMPS_SHIFT 0x0008
  28. #define WDTCON_ON BIT(15)
  29. #define WDTCON_CLR_KEY 0x5743
  30. /* Reset Control Register fields for watchdog */
  31. #define RESETCON_TIMEOUT_IDLE BIT(2)
  32. #define RESETCON_TIMEOUT_SLEEP BIT(3)
  33. #define RESETCON_WDT_TIMEOUT BIT(4)
  34. struct pic32_wdt {
  35. void __iomem *regs;
  36. void __iomem *rst_base;
  37. struct clk *clk;
  38. };
  39. static inline bool pic32_wdt_is_win_enabled(struct pic32_wdt *wdt)
  40. {
  41. return !!(readl(wdt->regs + WDTCON_REG) & WDTCON_WIN_EN);
  42. }
  43. static inline u32 pic32_wdt_get_post_scaler(struct pic32_wdt *wdt)
  44. {
  45. u32 v = readl(wdt->regs + WDTCON_REG);
  46. return (v >> WDTCON_RMPS_SHIFT) & WDTCON_RMPS_MASK;
  47. }
  48. static inline u32 pic32_wdt_get_clk_id(struct pic32_wdt *wdt)
  49. {
  50. u32 v = readl(wdt->regs + WDTCON_REG);
  51. return (v >> WDTCON_RMCS_SHIFT) & WDTCON_RMCS_MASK;
  52. }
  53. static int pic32_wdt_bootstatus(struct pic32_wdt *wdt)
  54. {
  55. u32 v = readl(wdt->rst_base);
  56. writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base));
  57. return v & RESETCON_WDT_TIMEOUT;
  58. }
  59. static u32 pic32_wdt_get_timeout_secs(struct pic32_wdt *wdt, struct device *dev)
  60. {
  61. unsigned long rate;
  62. u32 period, ps, terminal;
  63. rate = clk_get_rate(wdt->clk);
  64. dev_dbg(dev, "wdt: clk_id %d, clk_rate %lu (prescale)\n",
  65. pic32_wdt_get_clk_id(wdt), rate);
  66. /* default, prescaler of 32 (i.e. div-by-32) is implicit. */
  67. rate >>= 5;
  68. if (!rate)
  69. return 0;
  70. /* calculate terminal count from postscaler. */
  71. ps = pic32_wdt_get_post_scaler(wdt);
  72. terminal = BIT(ps);
  73. /* find time taken (in secs) to reach terminal count */
  74. period = terminal / rate;
  75. dev_dbg(dev,
  76. "wdt: clk_rate %lu (postscale) / terminal %d, timeout %dsec\n",
  77. rate, terminal, period);
  78. return period;
  79. }
  80. static void pic32_wdt_keepalive(struct pic32_wdt *wdt)
  81. {
  82. /* write key through single half-word */
  83. writew(WDTCON_CLR_KEY, wdt->regs + WDTCON_REG + 2);
  84. }
  85. static int pic32_wdt_start(struct watchdog_device *wdd)
  86. {
  87. struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
  88. writel(WDTCON_ON, PIC32_SET(wdt->regs + WDTCON_REG));
  89. pic32_wdt_keepalive(wdt);
  90. return 0;
  91. }
  92. static int pic32_wdt_stop(struct watchdog_device *wdd)
  93. {
  94. struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
  95. writel(WDTCON_ON, PIC32_CLR(wdt->regs + WDTCON_REG));
  96. /*
  97. * Cannot touch registers in the CPU cycle following clearing the
  98. * ON bit.
  99. */
  100. nop();
  101. return 0;
  102. }
  103. static int pic32_wdt_ping(struct watchdog_device *wdd)
  104. {
  105. struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
  106. pic32_wdt_keepalive(wdt);
  107. return 0;
  108. }
  109. static const struct watchdog_ops pic32_wdt_fops = {
  110. .owner = THIS_MODULE,
  111. .start = pic32_wdt_start,
  112. .stop = pic32_wdt_stop,
  113. .ping = pic32_wdt_ping,
  114. };
  115. static const struct watchdog_info pic32_wdt_ident = {
  116. .options = WDIOF_KEEPALIVEPING |
  117. WDIOF_MAGICCLOSE | WDIOF_CARDRESET,
  118. .identity = "PIC32 Watchdog",
  119. };
  120. static struct watchdog_device pic32_wdd = {
  121. .info = &pic32_wdt_ident,
  122. .ops = &pic32_wdt_fops,
  123. };
  124. static const struct of_device_id pic32_wdt_dt_ids[] = {
  125. { .compatible = "microchip,pic32mzda-wdt", },
  126. { /* sentinel */ }
  127. };
  128. MODULE_DEVICE_TABLE(of, pic32_wdt_dt_ids);
  129. static void pic32_clk_disable_unprepare(void *data)
  130. {
  131. clk_disable_unprepare(data);
  132. }
  133. static int pic32_wdt_drv_probe(struct platform_device *pdev)
  134. {
  135. struct device *dev = &pdev->dev;
  136. int ret;
  137. struct watchdog_device *wdd = &pic32_wdd;
  138. struct pic32_wdt *wdt;
  139. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  140. if (!wdt)
  141. return -ENOMEM;
  142. wdt->regs = devm_platform_ioremap_resource(pdev, 0);
  143. if (IS_ERR(wdt->regs))
  144. return PTR_ERR(wdt->regs);
  145. wdt->rst_base = devm_ioremap(dev, PIC32_BASE_RESET, 0x10);
  146. if (!wdt->rst_base)
  147. return -ENOMEM;
  148. wdt->clk = devm_clk_get(dev, NULL);
  149. if (IS_ERR(wdt->clk)) {
  150. dev_err(dev, "clk not found\n");
  151. return PTR_ERR(wdt->clk);
  152. }
  153. ret = clk_prepare_enable(wdt->clk);
  154. if (ret) {
  155. dev_err(dev, "clk enable failed\n");
  156. return ret;
  157. }
  158. ret = devm_add_action_or_reset(dev, pic32_clk_disable_unprepare,
  159. wdt->clk);
  160. if (ret)
  161. return ret;
  162. if (pic32_wdt_is_win_enabled(wdt)) {
  163. dev_err(dev, "windowed-clear mode is not supported.\n");
  164. return -ENODEV;
  165. }
  166. wdd->timeout = pic32_wdt_get_timeout_secs(wdt, dev);
  167. if (!wdd->timeout) {
  168. dev_err(dev, "failed to read watchdog register timeout\n");
  169. return -EINVAL;
  170. }
  171. dev_info(dev, "timeout %d\n", wdd->timeout);
  172. wdd->bootstatus = pic32_wdt_bootstatus(wdt) ? WDIOF_CARDRESET : 0;
  173. watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
  174. watchdog_set_drvdata(wdd, wdt);
  175. ret = devm_watchdog_register_device(dev, wdd);
  176. if (ret)
  177. return ret;
  178. platform_set_drvdata(pdev, wdd);
  179. return 0;
  180. }
  181. static struct platform_driver pic32_wdt_driver = {
  182. .probe = pic32_wdt_drv_probe,
  183. .driver = {
  184. .name = "pic32-wdt",
  185. .of_match_table = of_match_ptr(pic32_wdt_dt_ids),
  186. }
  187. };
  188. module_platform_driver(pic32_wdt_driver);
  189. MODULE_AUTHOR("Joshua Henderson <joshua.henderson@microchip.com>");
  190. MODULE_DESCRIPTION("Microchip PIC32 Watchdog Timer");
  191. MODULE_LICENSE("GPL");