pic32-dmt.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * PIC32 deadman timer driver
  4. *
  5. * Purna Chandra Mandal <purna.mandal@microchip.com>
  6. * Copyright (c) 2016, Microchip Technology Inc.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/device.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm.h>
  18. #include <linux/watchdog.h>
  19. #include <asm/mach-pic32/pic32.h>
  20. /* Deadman Timer Regs */
  21. #define DMTCON_REG 0x00
  22. #define DMTPRECLR_REG 0x10
  23. #define DMTCLR_REG 0x20
  24. #define DMTSTAT_REG 0x30
  25. #define DMTCNT_REG 0x40
  26. #define DMTPSCNT_REG 0x60
  27. #define DMTPSINTV_REG 0x70
  28. /* Deadman Timer Regs fields */
  29. #define DMT_ON BIT(15)
  30. #define DMT_STEP1_KEY BIT(6)
  31. #define DMT_STEP2_KEY BIT(3)
  32. #define DMTSTAT_WINOPN BIT(0)
  33. #define DMTSTAT_EVENT BIT(5)
  34. #define DMTSTAT_BAD2 BIT(6)
  35. #define DMTSTAT_BAD1 BIT(7)
  36. /* Reset Control Register fields for watchdog */
  37. #define RESETCON_DMT_TIMEOUT BIT(5)
  38. struct pic32_dmt {
  39. void __iomem *regs;
  40. struct clk *clk;
  41. };
  42. static inline void dmt_enable(struct pic32_dmt *dmt)
  43. {
  44. writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG));
  45. }
  46. static inline void dmt_disable(struct pic32_dmt *dmt)
  47. {
  48. writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG));
  49. /*
  50. * Cannot touch registers in the CPU cycle following clearing the
  51. * ON bit.
  52. */
  53. nop();
  54. }
  55. static inline int dmt_bad_status(struct pic32_dmt *dmt)
  56. {
  57. u32 val;
  58. val = readl(dmt->regs + DMTSTAT_REG);
  59. val &= (DMTSTAT_BAD1 | DMTSTAT_BAD2 | DMTSTAT_EVENT);
  60. if (val)
  61. return -EAGAIN;
  62. return 0;
  63. }
  64. static inline int dmt_keepalive(struct pic32_dmt *dmt)
  65. {
  66. u32 v;
  67. u32 timeout = 500;
  68. /* set pre-clear key */
  69. writel(DMT_STEP1_KEY << 8, dmt->regs + DMTPRECLR_REG);
  70. /* wait for DMT window to open */
  71. while (--timeout) {
  72. v = readl(dmt->regs + DMTSTAT_REG) & DMTSTAT_WINOPN;
  73. if (v == DMTSTAT_WINOPN)
  74. break;
  75. }
  76. /* apply key2 */
  77. writel(DMT_STEP2_KEY, dmt->regs + DMTCLR_REG);
  78. /* check whether keys are latched correctly */
  79. return dmt_bad_status(dmt);
  80. }
  81. static inline u32 pic32_dmt_get_timeout_secs(struct pic32_dmt *dmt)
  82. {
  83. unsigned long rate;
  84. rate = clk_get_rate(dmt->clk);
  85. if (rate)
  86. return readl(dmt->regs + DMTPSCNT_REG) / rate;
  87. return 0;
  88. }
  89. static inline u32 pic32_dmt_bootstatus(struct pic32_dmt *dmt)
  90. {
  91. u32 v;
  92. void __iomem *rst_base;
  93. rst_base = ioremap(PIC32_BASE_RESET, 0x10);
  94. if (!rst_base)
  95. return 0;
  96. v = readl(rst_base);
  97. writel(RESETCON_DMT_TIMEOUT, PIC32_CLR(rst_base));
  98. iounmap(rst_base);
  99. return v & RESETCON_DMT_TIMEOUT;
  100. }
  101. static int pic32_dmt_start(struct watchdog_device *wdd)
  102. {
  103. struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
  104. dmt_enable(dmt);
  105. return dmt_keepalive(dmt);
  106. }
  107. static int pic32_dmt_stop(struct watchdog_device *wdd)
  108. {
  109. struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
  110. dmt_disable(dmt);
  111. return 0;
  112. }
  113. static int pic32_dmt_ping(struct watchdog_device *wdd)
  114. {
  115. struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
  116. return dmt_keepalive(dmt);
  117. }
  118. static const struct watchdog_ops pic32_dmt_fops = {
  119. .owner = THIS_MODULE,
  120. .start = pic32_dmt_start,
  121. .stop = pic32_dmt_stop,
  122. .ping = pic32_dmt_ping,
  123. };
  124. static const struct watchdog_info pic32_dmt_ident = {
  125. .options = WDIOF_KEEPALIVEPING |
  126. WDIOF_MAGICCLOSE,
  127. .identity = "PIC32 Deadman Timer",
  128. };
  129. static struct watchdog_device pic32_dmt_wdd = {
  130. .info = &pic32_dmt_ident,
  131. .ops = &pic32_dmt_fops,
  132. };
  133. static void pic32_clk_disable_unprepare(void *data)
  134. {
  135. clk_disable_unprepare(data);
  136. }
  137. static int pic32_dmt_probe(struct platform_device *pdev)
  138. {
  139. struct device *dev = &pdev->dev;
  140. int ret;
  141. struct pic32_dmt *dmt;
  142. struct watchdog_device *wdd = &pic32_dmt_wdd;
  143. dmt = devm_kzalloc(dev, sizeof(*dmt), GFP_KERNEL);
  144. if (!dmt)
  145. return -ENOMEM;
  146. dmt->regs = devm_platform_ioremap_resource(pdev, 0);
  147. if (IS_ERR(dmt->regs))
  148. return PTR_ERR(dmt->regs);
  149. dmt->clk = devm_clk_get(dev, NULL);
  150. if (IS_ERR(dmt->clk)) {
  151. dev_err(dev, "clk not found\n");
  152. return PTR_ERR(dmt->clk);
  153. }
  154. ret = clk_prepare_enable(dmt->clk);
  155. if (ret)
  156. return ret;
  157. ret = devm_add_action_or_reset(dev, pic32_clk_disable_unprepare,
  158. dmt->clk);
  159. if (ret)
  160. return ret;
  161. wdd->timeout = pic32_dmt_get_timeout_secs(dmt);
  162. if (!wdd->timeout) {
  163. dev_err(dev, "failed to read watchdog register timeout\n");
  164. return -EINVAL;
  165. }
  166. dev_info(dev, "timeout %d\n", wdd->timeout);
  167. wdd->bootstatus = pic32_dmt_bootstatus(dmt) ? WDIOF_CARDRESET : 0;
  168. watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
  169. watchdog_set_drvdata(wdd, dmt);
  170. ret = devm_watchdog_register_device(dev, wdd);
  171. if (ret)
  172. return ret;
  173. platform_set_drvdata(pdev, wdd);
  174. return 0;
  175. }
  176. static const struct of_device_id pic32_dmt_of_ids[] = {
  177. { .compatible = "microchip,pic32mzda-dmt",},
  178. { /* sentinel */ }
  179. };
  180. MODULE_DEVICE_TABLE(of, pic32_dmt_of_ids);
  181. static struct platform_driver pic32_dmt_driver = {
  182. .probe = pic32_dmt_probe,
  183. .driver = {
  184. .name = "pic32-dmt",
  185. .of_match_table = of_match_ptr(pic32_dmt_of_ids),
  186. }
  187. };
  188. module_platform_driver(pic32_dmt_driver);
  189. MODULE_AUTHOR("Purna Chandra Mandal <purna.mandal@microchip.com>");
  190. MODULE_DESCRIPTION("Microchip PIC32 DMT Driver");
  191. MODULE_LICENSE("GPL");