npcm_wdt.c 5.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249
  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2018 Nuvoton Technology corporation.
  3. // Copyright (c) 2018 IBM Corp.
  4. #include <linux/bitops.h>
  5. #include <linux/delay.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/of_irq.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/slab.h>
  12. #include <linux/watchdog.h>
  13. #define NPCM_WTCR 0x1C
  14. #define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */
  15. #define NPCM_WTE BIT(7) /* Enable */
  16. #define NPCM_WTIE BIT(6) /* Enable irq */
  17. #define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */
  18. #define NPCM_WTIF BIT(3) /* Interrupt flag*/
  19. #define NPCM_WTRF BIT(2) /* Reset flag */
  20. #define NPCM_WTRE BIT(1) /* Reset enable */
  21. #define NPCM_WTR BIT(0) /* Reset counter */
  22. /*
  23. * Watchdog timeouts
  24. *
  25. * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
  26. * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
  27. * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
  28. * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
  29. * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
  30. * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
  31. * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
  32. * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
  33. * 85600 msec: WTCLK=10 WTIS=11 VAL= 0x830
  34. * 172000 msec: WTCLK=11 WTIS=01 VAL= 0xC10
  35. * 687000 msec: WTCLK=11 WTIS=10 VAL= 0xC20
  36. * 2750000 msec: WTCLK=11 WTIS=11 VAL= 0xC30
  37. */
  38. struct npcm_wdt {
  39. struct watchdog_device wdd;
  40. void __iomem *reg;
  41. };
  42. static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd)
  43. {
  44. return container_of(wdd, struct npcm_wdt, wdd);
  45. }
  46. static int npcm_wdt_ping(struct watchdog_device *wdd)
  47. {
  48. struct npcm_wdt *wdt = to_npcm_wdt(wdd);
  49. u32 val;
  50. val = readl(wdt->reg);
  51. writel(val | NPCM_WTR, wdt->reg);
  52. return 0;
  53. }
  54. static int npcm_wdt_start(struct watchdog_device *wdd)
  55. {
  56. struct npcm_wdt *wdt = to_npcm_wdt(wdd);
  57. u32 val;
  58. if (wdd->timeout < 2)
  59. val = 0x800;
  60. else if (wdd->timeout < 3)
  61. val = 0x420;
  62. else if (wdd->timeout < 6)
  63. val = 0x810;
  64. else if (wdd->timeout < 11)
  65. val = 0x430;
  66. else if (wdd->timeout < 22)
  67. val = 0x820;
  68. else if (wdd->timeout < 44)
  69. val = 0xC00;
  70. else if (wdd->timeout < 87)
  71. val = 0x830;
  72. else if (wdd->timeout < 173)
  73. val = 0xC10;
  74. else if (wdd->timeout < 688)
  75. val = 0xC20;
  76. else
  77. val = 0xC30;
  78. val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE;
  79. writel(val, wdt->reg);
  80. return 0;
  81. }
  82. static int npcm_wdt_stop(struct watchdog_device *wdd)
  83. {
  84. struct npcm_wdt *wdt = to_npcm_wdt(wdd);
  85. writel(0, wdt->reg);
  86. return 0;
  87. }
  88. static int npcm_wdt_set_timeout(struct watchdog_device *wdd,
  89. unsigned int timeout)
  90. {
  91. if (timeout < 2)
  92. wdd->timeout = 1;
  93. else if (timeout < 3)
  94. wdd->timeout = 2;
  95. else if (timeout < 6)
  96. wdd->timeout = 5;
  97. else if (timeout < 11)
  98. wdd->timeout = 10;
  99. else if (timeout < 22)
  100. wdd->timeout = 21;
  101. else if (timeout < 44)
  102. wdd->timeout = 43;
  103. else if (timeout < 87)
  104. wdd->timeout = 86;
  105. else if (timeout < 173)
  106. wdd->timeout = 172;
  107. else if (timeout < 688)
  108. wdd->timeout = 687;
  109. else
  110. wdd->timeout = 2750;
  111. if (watchdog_active(wdd))
  112. npcm_wdt_start(wdd);
  113. return 0;
  114. }
  115. static irqreturn_t npcm_wdt_interrupt(int irq, void *data)
  116. {
  117. struct npcm_wdt *wdt = data;
  118. watchdog_notify_pretimeout(&wdt->wdd);
  119. return IRQ_HANDLED;
  120. }
  121. static int npcm_wdt_restart(struct watchdog_device *wdd,
  122. unsigned long action, void *data)
  123. {
  124. struct npcm_wdt *wdt = to_npcm_wdt(wdd);
  125. writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg);
  126. udelay(1000);
  127. return 0;
  128. }
  129. static bool npcm_is_running(struct watchdog_device *wdd)
  130. {
  131. struct npcm_wdt *wdt = to_npcm_wdt(wdd);
  132. return readl(wdt->reg) & NPCM_WTE;
  133. }
  134. static const struct watchdog_info npcm_wdt_info = {
  135. .identity = KBUILD_MODNAME,
  136. .options = WDIOF_SETTIMEOUT
  137. | WDIOF_KEEPALIVEPING
  138. | WDIOF_MAGICCLOSE,
  139. };
  140. static const struct watchdog_ops npcm_wdt_ops = {
  141. .owner = THIS_MODULE,
  142. .start = npcm_wdt_start,
  143. .stop = npcm_wdt_stop,
  144. .ping = npcm_wdt_ping,
  145. .set_timeout = npcm_wdt_set_timeout,
  146. .restart = npcm_wdt_restart,
  147. };
  148. static int npcm_wdt_probe(struct platform_device *pdev)
  149. {
  150. struct device *dev = &pdev->dev;
  151. struct npcm_wdt *wdt;
  152. int irq;
  153. int ret;
  154. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  155. if (!wdt)
  156. return -ENOMEM;
  157. wdt->reg = devm_platform_ioremap_resource(pdev, 0);
  158. if (IS_ERR(wdt->reg))
  159. return PTR_ERR(wdt->reg);
  160. irq = platform_get_irq(pdev, 0);
  161. if (irq < 0)
  162. return irq;
  163. wdt->wdd.info = &npcm_wdt_info;
  164. wdt->wdd.ops = &npcm_wdt_ops;
  165. wdt->wdd.min_timeout = 1;
  166. wdt->wdd.max_timeout = 2750;
  167. wdt->wdd.parent = dev;
  168. wdt->wdd.timeout = 86;
  169. watchdog_init_timeout(&wdt->wdd, 0, dev);
  170. /* Ensure timeout is able to be represented by the hardware */
  171. npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
  172. if (npcm_is_running(&wdt->wdd)) {
  173. /* Restart with the default or device-tree specified timeout */
  174. npcm_wdt_start(&wdt->wdd);
  175. set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
  176. }
  177. ret = devm_request_irq(dev, irq, npcm_wdt_interrupt, 0, "watchdog",
  178. wdt);
  179. if (ret)
  180. return ret;
  181. ret = devm_watchdog_register_device(dev, &wdt->wdd);
  182. if (ret)
  183. return ret;
  184. dev_info(dev, "NPCM watchdog driver enabled\n");
  185. return 0;
  186. }
  187. #ifdef CONFIG_OF
  188. static const struct of_device_id npcm_wdt_match[] = {
  189. {.compatible = "nuvoton,npcm750-wdt"},
  190. {},
  191. };
  192. MODULE_DEVICE_TABLE(of, npcm_wdt_match);
  193. #endif
  194. static struct platform_driver npcm_wdt_driver = {
  195. .probe = npcm_wdt_probe,
  196. .driver = {
  197. .name = "npcm-wdt",
  198. .of_match_table = of_match_ptr(npcm_wdt_match),
  199. },
  200. };
  201. module_platform_driver(npcm_wdt_driver);
  202. MODULE_AUTHOR("Joel Stanley");
  203. MODULE_DESCRIPTION("Watchdog driver for NPCM");
  204. MODULE_LICENSE("GPL v2");