max77620_wdt.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Maxim MAX77620 Watchdog Driver
  4. *
  5. * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
  6. *
  7. * Author: Laxman Dewangan <ldewangan@nvidia.com>
  8. */
  9. #include <linux/err.h>
  10. #include <linux/init.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/mod_devicetable.h>
  14. #include <linux/mfd/max77620.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #include <linux/watchdog.h>
  19. static bool nowayout = WATCHDOG_NOWAYOUT;
  20. struct max77620_wdt {
  21. struct device *dev;
  22. struct regmap *rmap;
  23. struct watchdog_device wdt_dev;
  24. };
  25. static int max77620_wdt_start(struct watchdog_device *wdt_dev)
  26. {
  27. struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
  28. return regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
  29. MAX77620_WDTEN, MAX77620_WDTEN);
  30. }
  31. static int max77620_wdt_stop(struct watchdog_device *wdt_dev)
  32. {
  33. struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
  34. return regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
  35. MAX77620_WDTEN, 0);
  36. }
  37. static int max77620_wdt_ping(struct watchdog_device *wdt_dev)
  38. {
  39. struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
  40. return regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL3,
  41. MAX77620_WDTC_MASK, 0x1);
  42. }
  43. static int max77620_wdt_set_timeout(struct watchdog_device *wdt_dev,
  44. unsigned int timeout)
  45. {
  46. struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
  47. unsigned int wdt_timeout;
  48. u8 regval;
  49. int ret;
  50. switch (timeout) {
  51. case 0 ... 2:
  52. regval = MAX77620_TWD_2s;
  53. wdt_timeout = 2;
  54. break;
  55. case 3 ... 16:
  56. regval = MAX77620_TWD_16s;
  57. wdt_timeout = 16;
  58. break;
  59. case 17 ... 64:
  60. regval = MAX77620_TWD_64s;
  61. wdt_timeout = 64;
  62. break;
  63. default:
  64. regval = MAX77620_TWD_128s;
  65. wdt_timeout = 128;
  66. break;
  67. }
  68. ret = regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL3,
  69. MAX77620_WDTC_MASK, 0x1);
  70. if (ret < 0)
  71. return ret;
  72. ret = regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
  73. MAX77620_TWD_MASK, regval);
  74. if (ret < 0)
  75. return ret;
  76. wdt_dev->timeout = wdt_timeout;
  77. return 0;
  78. }
  79. static const struct watchdog_info max77620_wdt_info = {
  80. .identity = "max77620-watchdog",
  81. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  82. };
  83. static const struct watchdog_ops max77620_wdt_ops = {
  84. .start = max77620_wdt_start,
  85. .stop = max77620_wdt_stop,
  86. .ping = max77620_wdt_ping,
  87. .set_timeout = max77620_wdt_set_timeout,
  88. };
  89. static int max77620_wdt_probe(struct platform_device *pdev)
  90. {
  91. struct device *dev = &pdev->dev;
  92. struct max77620_wdt *wdt;
  93. struct watchdog_device *wdt_dev;
  94. unsigned int regval;
  95. int ret;
  96. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  97. if (!wdt)
  98. return -ENOMEM;
  99. wdt->dev = dev;
  100. wdt->rmap = dev_get_regmap(dev->parent, NULL);
  101. if (!wdt->rmap) {
  102. dev_err(wdt->dev, "Failed to get parent regmap\n");
  103. return -ENODEV;
  104. }
  105. wdt_dev = &wdt->wdt_dev;
  106. wdt_dev->info = &max77620_wdt_info;
  107. wdt_dev->ops = &max77620_wdt_ops;
  108. wdt_dev->min_timeout = 2;
  109. wdt_dev->max_timeout = 128;
  110. wdt_dev->max_hw_heartbeat_ms = 128 * 1000;
  111. platform_set_drvdata(pdev, wdt);
  112. /* Enable WD_RST_WK - WDT expire results in a restart */
  113. ret = regmap_update_bits(wdt->rmap, MAX77620_REG_ONOFFCNFG2,
  114. MAX77620_ONOFFCNFG2_WD_RST_WK,
  115. MAX77620_ONOFFCNFG2_WD_RST_WK);
  116. if (ret < 0) {
  117. dev_err(wdt->dev, "Failed to set WD_RST_WK: %d\n", ret);
  118. return ret;
  119. }
  120. /* Set WDT clear in OFF and sleep mode */
  121. ret = regmap_update_bits(wdt->rmap, MAX77620_REG_CNFGGLBL2,
  122. MAX77620_WDTOFFC | MAX77620_WDTSLPC,
  123. MAX77620_WDTOFFC | MAX77620_WDTSLPC);
  124. if (ret < 0) {
  125. dev_err(wdt->dev, "Failed to set WDT OFF mode: %d\n", ret);
  126. return ret;
  127. }
  128. /* Check if WDT running and if yes then set flags properly */
  129. ret = regmap_read(wdt->rmap, MAX77620_REG_CNFGGLBL2, &regval);
  130. if (ret < 0) {
  131. dev_err(wdt->dev, "Failed to read WDT CFG register: %d\n", ret);
  132. return ret;
  133. }
  134. switch (regval & MAX77620_TWD_MASK) {
  135. case MAX77620_TWD_2s:
  136. wdt_dev->timeout = 2;
  137. break;
  138. case MAX77620_TWD_16s:
  139. wdt_dev->timeout = 16;
  140. break;
  141. case MAX77620_TWD_64s:
  142. wdt_dev->timeout = 64;
  143. break;
  144. default:
  145. wdt_dev->timeout = 128;
  146. break;
  147. }
  148. if (regval & MAX77620_WDTEN)
  149. set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
  150. watchdog_set_nowayout(wdt_dev, nowayout);
  151. watchdog_set_drvdata(wdt_dev, wdt);
  152. watchdog_stop_on_unregister(wdt_dev);
  153. return devm_watchdog_register_device(dev, wdt_dev);
  154. }
  155. static const struct platform_device_id max77620_wdt_devtype[] = {
  156. { .name = "max77620-watchdog", },
  157. { },
  158. };
  159. MODULE_DEVICE_TABLE(platform, max77620_wdt_devtype);
  160. static struct platform_driver max77620_wdt_driver = {
  161. .driver = {
  162. .name = "max77620-watchdog",
  163. },
  164. .probe = max77620_wdt_probe,
  165. .id_table = max77620_wdt_devtype,
  166. };
  167. module_platform_driver(max77620_wdt_driver);
  168. MODULE_DESCRIPTION("Max77620 watchdog timer driver");
  169. module_param(nowayout, bool, 0);
  170. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  171. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  172. MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
  173. MODULE_LICENSE("GPL v2");