lpc18xx_wdt.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * NXP LPC18xx Watchdog Timer (WDT)
  4. *
  5. * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
  6. *
  7. * Notes
  8. * -----
  9. * The Watchdog consists of a fixed divide-by-4 clock pre-scaler and a 24-bit
  10. * counter which decrements on every clock cycle.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/watchdog.h>
  18. /* Registers */
  19. #define LPC18XX_WDT_MOD 0x00
  20. #define LPC18XX_WDT_MOD_WDEN BIT(0)
  21. #define LPC18XX_WDT_MOD_WDRESET BIT(1)
  22. #define LPC18XX_WDT_TC 0x04
  23. #define LPC18XX_WDT_TC_MIN 0xff
  24. #define LPC18XX_WDT_TC_MAX 0xffffff
  25. #define LPC18XX_WDT_FEED 0x08
  26. #define LPC18XX_WDT_FEED_MAGIC1 0xaa
  27. #define LPC18XX_WDT_FEED_MAGIC2 0x55
  28. #define LPC18XX_WDT_TV 0x0c
  29. /* Clock pre-scaler */
  30. #define LPC18XX_WDT_CLK_DIV 4
  31. /* Timeout values in seconds */
  32. #define LPC18XX_WDT_DEF_TIMEOUT 30U
  33. static int heartbeat;
  34. module_param(heartbeat, int, 0);
  35. MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds (default="
  36. __MODULE_STRING(LPC18XX_WDT_DEF_TIMEOUT) ")");
  37. static bool nowayout = WATCHDOG_NOWAYOUT;
  38. module_param(nowayout, bool, 0);
  39. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  40. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  41. struct lpc18xx_wdt_dev {
  42. struct watchdog_device wdt_dev;
  43. struct clk *reg_clk;
  44. struct clk *wdt_clk;
  45. unsigned long clk_rate;
  46. void __iomem *base;
  47. struct timer_list timer;
  48. spinlock_t lock;
  49. };
  50. static int lpc18xx_wdt_feed(struct watchdog_device *wdt_dev)
  51. {
  52. struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
  53. unsigned long flags;
  54. /*
  55. * An abort condition will occur if an interrupt happens during the feed
  56. * sequence.
  57. */
  58. spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
  59. writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
  60. writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
  61. spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
  62. return 0;
  63. }
  64. static void lpc18xx_wdt_timer_feed(struct timer_list *t)
  65. {
  66. struct lpc18xx_wdt_dev *lpc18xx_wdt = from_timer(lpc18xx_wdt, t, timer);
  67. struct watchdog_device *wdt_dev = &lpc18xx_wdt->wdt_dev;
  68. lpc18xx_wdt_feed(wdt_dev);
  69. /* Use safe value (1/2 of real timeout) */
  70. mod_timer(&lpc18xx_wdt->timer, jiffies +
  71. msecs_to_jiffies((wdt_dev->timeout * MSEC_PER_SEC) / 2));
  72. }
  73. /*
  74. * Since LPC18xx Watchdog cannot be disabled in hardware, we must keep feeding
  75. * it with a timer until userspace watchdog software takes over.
  76. */
  77. static int lpc18xx_wdt_stop(struct watchdog_device *wdt_dev)
  78. {
  79. struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
  80. lpc18xx_wdt_timer_feed(&lpc18xx_wdt->timer);
  81. return 0;
  82. }
  83. static void __lpc18xx_wdt_set_timeout(struct lpc18xx_wdt_dev *lpc18xx_wdt)
  84. {
  85. unsigned int val;
  86. val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate,
  87. LPC18XX_WDT_CLK_DIV);
  88. writel(val, lpc18xx_wdt->base + LPC18XX_WDT_TC);
  89. }
  90. static int lpc18xx_wdt_set_timeout(struct watchdog_device *wdt_dev,
  91. unsigned int new_timeout)
  92. {
  93. struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
  94. lpc18xx_wdt->wdt_dev.timeout = new_timeout;
  95. __lpc18xx_wdt_set_timeout(lpc18xx_wdt);
  96. return 0;
  97. }
  98. static unsigned int lpc18xx_wdt_get_timeleft(struct watchdog_device *wdt_dev)
  99. {
  100. struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
  101. unsigned int val;
  102. val = readl(lpc18xx_wdt->base + LPC18XX_WDT_TV);
  103. return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
  104. }
  105. static int lpc18xx_wdt_start(struct watchdog_device *wdt_dev)
  106. {
  107. struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
  108. unsigned int val;
  109. if (timer_pending(&lpc18xx_wdt->timer))
  110. del_timer(&lpc18xx_wdt->timer);
  111. val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
  112. val |= LPC18XX_WDT_MOD_WDEN;
  113. val |= LPC18XX_WDT_MOD_WDRESET;
  114. writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
  115. /*
  116. * Setting the WDEN bit in the WDMOD register is not sufficient to
  117. * enable the Watchdog. A valid feed sequence must be completed after
  118. * setting WDEN before the Watchdog is capable of generating a reset.
  119. */
  120. lpc18xx_wdt_feed(wdt_dev);
  121. return 0;
  122. }
  123. static int lpc18xx_wdt_restart(struct watchdog_device *wdt_dev,
  124. unsigned long action, void *data)
  125. {
  126. struct lpc18xx_wdt_dev *lpc18xx_wdt = watchdog_get_drvdata(wdt_dev);
  127. unsigned long flags;
  128. int val;
  129. /*
  130. * Incorrect feed sequence causes immediate watchdog reset if enabled.
  131. */
  132. spin_lock_irqsave(&lpc18xx_wdt->lock, flags);
  133. val = readl(lpc18xx_wdt->base + LPC18XX_WDT_MOD);
  134. val |= LPC18XX_WDT_MOD_WDEN;
  135. val |= LPC18XX_WDT_MOD_WDRESET;
  136. writel(val, lpc18xx_wdt->base + LPC18XX_WDT_MOD);
  137. writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
  138. writel(LPC18XX_WDT_FEED_MAGIC2, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
  139. writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
  140. writel(LPC18XX_WDT_FEED_MAGIC1, lpc18xx_wdt->base + LPC18XX_WDT_FEED);
  141. spin_unlock_irqrestore(&lpc18xx_wdt->lock, flags);
  142. return 0;
  143. }
  144. static const struct watchdog_info lpc18xx_wdt_info = {
  145. .identity = "NXP LPC18xx Watchdog",
  146. .options = WDIOF_SETTIMEOUT |
  147. WDIOF_KEEPALIVEPING |
  148. WDIOF_MAGICCLOSE,
  149. };
  150. static const struct watchdog_ops lpc18xx_wdt_ops = {
  151. .owner = THIS_MODULE,
  152. .start = lpc18xx_wdt_start,
  153. .stop = lpc18xx_wdt_stop,
  154. .ping = lpc18xx_wdt_feed,
  155. .set_timeout = lpc18xx_wdt_set_timeout,
  156. .get_timeleft = lpc18xx_wdt_get_timeleft,
  157. .restart = lpc18xx_wdt_restart,
  158. };
  159. static void lpc18xx_clk_disable_unprepare(void *data)
  160. {
  161. clk_disable_unprepare(data);
  162. }
  163. static int lpc18xx_wdt_probe(struct platform_device *pdev)
  164. {
  165. struct lpc18xx_wdt_dev *lpc18xx_wdt;
  166. struct device *dev = &pdev->dev;
  167. int ret;
  168. lpc18xx_wdt = devm_kzalloc(dev, sizeof(*lpc18xx_wdt), GFP_KERNEL);
  169. if (!lpc18xx_wdt)
  170. return -ENOMEM;
  171. lpc18xx_wdt->base = devm_platform_ioremap_resource(pdev, 0);
  172. if (IS_ERR(lpc18xx_wdt->base))
  173. return PTR_ERR(lpc18xx_wdt->base);
  174. lpc18xx_wdt->reg_clk = devm_clk_get(dev, "reg");
  175. if (IS_ERR(lpc18xx_wdt->reg_clk)) {
  176. dev_err(dev, "failed to get the reg clock\n");
  177. return PTR_ERR(lpc18xx_wdt->reg_clk);
  178. }
  179. lpc18xx_wdt->wdt_clk = devm_clk_get(dev, "wdtclk");
  180. if (IS_ERR(lpc18xx_wdt->wdt_clk)) {
  181. dev_err(dev, "failed to get the wdt clock\n");
  182. return PTR_ERR(lpc18xx_wdt->wdt_clk);
  183. }
  184. ret = clk_prepare_enable(lpc18xx_wdt->reg_clk);
  185. if (ret) {
  186. dev_err(dev, "could not prepare or enable sys clock\n");
  187. return ret;
  188. }
  189. ret = devm_add_action_or_reset(dev, lpc18xx_clk_disable_unprepare,
  190. lpc18xx_wdt->reg_clk);
  191. if (ret)
  192. return ret;
  193. ret = clk_prepare_enable(lpc18xx_wdt->wdt_clk);
  194. if (ret) {
  195. dev_err(dev, "could not prepare or enable wdt clock\n");
  196. return ret;
  197. }
  198. ret = devm_add_action_or_reset(dev, lpc18xx_clk_disable_unprepare,
  199. lpc18xx_wdt->wdt_clk);
  200. if (ret)
  201. return ret;
  202. /* We use the clock rate to calculate timeouts */
  203. lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk);
  204. if (lpc18xx_wdt->clk_rate == 0) {
  205. dev_err(dev, "failed to get clock rate\n");
  206. return -EINVAL;
  207. }
  208. lpc18xx_wdt->wdt_dev.info = &lpc18xx_wdt_info;
  209. lpc18xx_wdt->wdt_dev.ops = &lpc18xx_wdt_ops;
  210. lpc18xx_wdt->wdt_dev.min_timeout = DIV_ROUND_UP(LPC18XX_WDT_TC_MIN *
  211. LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate);
  212. lpc18xx_wdt->wdt_dev.max_timeout = (LPC18XX_WDT_TC_MAX *
  213. LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate;
  214. lpc18xx_wdt->wdt_dev.timeout = min(lpc18xx_wdt->wdt_dev.max_timeout,
  215. LPC18XX_WDT_DEF_TIMEOUT);
  216. spin_lock_init(&lpc18xx_wdt->lock);
  217. lpc18xx_wdt->wdt_dev.parent = dev;
  218. watchdog_set_drvdata(&lpc18xx_wdt->wdt_dev, lpc18xx_wdt);
  219. watchdog_init_timeout(&lpc18xx_wdt->wdt_dev, heartbeat, dev);
  220. __lpc18xx_wdt_set_timeout(lpc18xx_wdt);
  221. timer_setup(&lpc18xx_wdt->timer, lpc18xx_wdt_timer_feed, 0);
  222. watchdog_set_nowayout(&lpc18xx_wdt->wdt_dev, nowayout);
  223. watchdog_set_restart_priority(&lpc18xx_wdt->wdt_dev, 128);
  224. platform_set_drvdata(pdev, lpc18xx_wdt);
  225. watchdog_stop_on_reboot(&lpc18xx_wdt->wdt_dev);
  226. return devm_watchdog_register_device(dev, &lpc18xx_wdt->wdt_dev);
  227. }
  228. static int lpc18xx_wdt_remove(struct platform_device *pdev)
  229. {
  230. struct lpc18xx_wdt_dev *lpc18xx_wdt = platform_get_drvdata(pdev);
  231. dev_warn(&pdev->dev, "I quit now, hardware will probably reboot!\n");
  232. del_timer_sync(&lpc18xx_wdt->timer);
  233. return 0;
  234. }
  235. static const struct of_device_id lpc18xx_wdt_match[] = {
  236. { .compatible = "nxp,lpc1850-wwdt" },
  237. {}
  238. };
  239. MODULE_DEVICE_TABLE(of, lpc18xx_wdt_match);
  240. static struct platform_driver lpc18xx_wdt_driver = {
  241. .driver = {
  242. .name = "lpc18xx-wdt",
  243. .of_match_table = lpc18xx_wdt_match,
  244. },
  245. .probe = lpc18xx_wdt_probe,
  246. .remove = lpc18xx_wdt_remove,
  247. };
  248. module_platform_driver(lpc18xx_wdt_driver);
  249. MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
  250. MODULE_DESCRIPTION("NXP LPC18xx Watchdog Timer Driver");
  251. MODULE_LICENSE("GPL v2");