lantiq_wdt.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2010 John Crispin <john@phrozen.org>
  5. * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
  6. * Based on EP93xx wdt driver
  7. */
  8. #include <linux/module.h>
  9. #include <linux/bitops.h>
  10. #include <linux/watchdog.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/uaccess.h>
  13. #include <linux/clk.h>
  14. #include <linux/io.h>
  15. #include <linux/regmap.h>
  16. #include <linux/mfd/syscon.h>
  17. #include <lantiq_soc.h>
  18. #define LTQ_XRX_RCU_RST_STAT 0x0014
  19. #define LTQ_XRX_RCU_RST_STAT_WDT BIT(31)
  20. /* CPU0 Reset Source Register */
  21. #define LTQ_FALCON_SYS1_CPU0RS 0x0060
  22. /* reset cause mask */
  23. #define LTQ_FALCON_SYS1_CPU0RS_MASK 0x0007
  24. #define LTQ_FALCON_SYS1_CPU0RS_WDT 0x02
  25. /*
  26. * Section 3.4 of the datasheet
  27. * The password sequence protects the WDT control register from unintended
  28. * write actions, which might cause malfunction of the WDT.
  29. *
  30. * essentially the following two magic passwords need to be written to allow
  31. * IO access to the WDT core
  32. */
  33. #define LTQ_WDT_CR_PW1 0x00BE0000
  34. #define LTQ_WDT_CR_PW2 0x00DC0000
  35. #define LTQ_WDT_CR 0x0 /* watchdog control register */
  36. #define LTQ_WDT_CR_GEN BIT(31) /* enable bit */
  37. /* Pre-warning limit set to 1/16 of max WDT period */
  38. #define LTQ_WDT_CR_PWL (0x3 << 26)
  39. /* set clock divider to 0x40000 */
  40. #define LTQ_WDT_CR_CLKDIV (0x3 << 24)
  41. #define LTQ_WDT_CR_PW_MASK GENMASK(23, 16) /* Password field */
  42. #define LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
  43. #define LTQ_WDT_SR 0x8 /* watchdog status register */
  44. #define LTQ_WDT_SR_EN BIT(31) /* Enable */
  45. #define LTQ_WDT_SR_VALUE_MASK GENMASK(15, 0) /* Timer value */
  46. #define LTQ_WDT_DIVIDER 0x40000
  47. static bool nowayout = WATCHDOG_NOWAYOUT;
  48. struct ltq_wdt_hw {
  49. int (*bootstatus_get)(struct device *dev);
  50. };
  51. struct ltq_wdt_priv {
  52. struct watchdog_device wdt;
  53. void __iomem *membase;
  54. unsigned long clk_rate;
  55. };
  56. static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
  57. {
  58. return __raw_readl(priv->membase + offset);
  59. }
  60. static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
  61. {
  62. __raw_writel(val, priv->membase + offset);
  63. }
  64. static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
  65. u32 offset)
  66. {
  67. u32 val = ltq_wdt_r32(priv, offset);
  68. val &= ~(clear);
  69. val |= set;
  70. ltq_wdt_w32(priv, val, offset);
  71. }
  72. static struct ltq_wdt_priv *ltq_wdt_get_priv(struct watchdog_device *wdt)
  73. {
  74. return container_of(wdt, struct ltq_wdt_priv, wdt);
  75. }
  76. static struct watchdog_info ltq_wdt_info = {
  77. .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
  78. WDIOF_CARDRESET,
  79. .identity = "ltq_wdt",
  80. };
  81. static int ltq_wdt_start(struct watchdog_device *wdt)
  82. {
  83. struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
  84. u32 timeout;
  85. timeout = wdt->timeout * priv->clk_rate;
  86. ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
  87. /* write the second magic plus the configuration and new timeout */
  88. ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
  89. LTQ_WDT_CR_GEN | LTQ_WDT_CR_PWL | LTQ_WDT_CR_CLKDIV |
  90. LTQ_WDT_CR_PW2 | timeout,
  91. LTQ_WDT_CR);
  92. return 0;
  93. }
  94. static int ltq_wdt_stop(struct watchdog_device *wdt)
  95. {
  96. struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
  97. ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
  98. ltq_wdt_mask(priv, LTQ_WDT_CR_GEN | LTQ_WDT_CR_PW_MASK,
  99. LTQ_WDT_CR_PW2, LTQ_WDT_CR);
  100. return 0;
  101. }
  102. static int ltq_wdt_ping(struct watchdog_device *wdt)
  103. {
  104. struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
  105. u32 timeout;
  106. timeout = wdt->timeout * priv->clk_rate;
  107. ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
  108. /* write the second magic plus the configuration and new timeout */
  109. ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
  110. LTQ_WDT_CR_PW2 | timeout, LTQ_WDT_CR);
  111. return 0;
  112. }
  113. static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
  114. {
  115. struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
  116. u64 timeout;
  117. timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
  118. return do_div(timeout, priv->clk_rate);
  119. }
  120. static const struct watchdog_ops ltq_wdt_ops = {
  121. .owner = THIS_MODULE,
  122. .start = ltq_wdt_start,
  123. .stop = ltq_wdt_stop,
  124. .ping = ltq_wdt_ping,
  125. .get_timeleft = ltq_wdt_get_timeleft,
  126. };
  127. static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
  128. {
  129. struct regmap *rcu_regmap;
  130. u32 val;
  131. int err;
  132. rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
  133. if (IS_ERR(rcu_regmap))
  134. return PTR_ERR(rcu_regmap);
  135. err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
  136. if (err)
  137. return err;
  138. if (val & LTQ_XRX_RCU_RST_STAT_WDT)
  139. return WDIOF_CARDRESET;
  140. return 0;
  141. }
  142. static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
  143. {
  144. struct regmap *rcu_regmap;
  145. u32 val;
  146. int err;
  147. rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
  148. "lantiq,rcu");
  149. if (IS_ERR(rcu_regmap))
  150. return PTR_ERR(rcu_regmap);
  151. err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
  152. if (err)
  153. return err;
  154. if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
  155. return WDIOF_CARDRESET;
  156. return 0;
  157. }
  158. static int ltq_wdt_probe(struct platform_device *pdev)
  159. {
  160. struct device *dev = &pdev->dev;
  161. struct ltq_wdt_priv *priv;
  162. struct watchdog_device *wdt;
  163. struct clk *clk;
  164. const struct ltq_wdt_hw *ltq_wdt_hw;
  165. int ret;
  166. u32 status;
  167. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  168. if (!priv)
  169. return -ENOMEM;
  170. priv->membase = devm_platform_ioremap_resource(pdev, 0);
  171. if (IS_ERR(priv->membase))
  172. return PTR_ERR(priv->membase);
  173. /* we do not need to enable the clock as it is always running */
  174. clk = clk_get_io();
  175. priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
  176. if (!priv->clk_rate) {
  177. dev_err(dev, "clock rate less than divider %i\n",
  178. LTQ_WDT_DIVIDER);
  179. return -EINVAL;
  180. }
  181. wdt = &priv->wdt;
  182. wdt->info = &ltq_wdt_info;
  183. wdt->ops = &ltq_wdt_ops;
  184. wdt->min_timeout = 1;
  185. wdt->max_timeout = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
  186. wdt->timeout = wdt->max_timeout;
  187. wdt->parent = dev;
  188. ltq_wdt_hw = of_device_get_match_data(dev);
  189. if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
  190. ret = ltq_wdt_hw->bootstatus_get(dev);
  191. if (ret >= 0)
  192. wdt->bootstatus = ret;
  193. }
  194. watchdog_set_nowayout(wdt, nowayout);
  195. watchdog_init_timeout(wdt, 0, dev);
  196. status = ltq_wdt_r32(priv, LTQ_WDT_SR);
  197. if (status & LTQ_WDT_SR_EN) {
  198. /*
  199. * If the watchdog is already running overwrite it with our
  200. * new settings. Stop is not needed as the start call will
  201. * replace all settings anyway.
  202. */
  203. ltq_wdt_start(wdt);
  204. set_bit(WDOG_HW_RUNNING, &wdt->status);
  205. }
  206. return devm_watchdog_register_device(dev, wdt);
  207. }
  208. static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
  209. .bootstatus_get = ltq_wdt_xrx_bootstatus_get,
  210. };
  211. static const struct ltq_wdt_hw ltq_wdt_falcon = {
  212. .bootstatus_get = ltq_wdt_falcon_bootstatus_get,
  213. };
  214. static const struct of_device_id ltq_wdt_match[] = {
  215. { .compatible = "lantiq,wdt", .data = NULL },
  216. { .compatible = "lantiq,xrx100-wdt", .data = &ltq_wdt_xrx100 },
  217. { .compatible = "lantiq,falcon-wdt", .data = &ltq_wdt_falcon },
  218. {},
  219. };
  220. MODULE_DEVICE_TABLE(of, ltq_wdt_match);
  221. static struct platform_driver ltq_wdt_driver = {
  222. .probe = ltq_wdt_probe,
  223. .driver = {
  224. .name = "wdt",
  225. .of_match_table = ltq_wdt_match,
  226. },
  227. };
  228. module_platform_driver(ltq_wdt_driver);
  229. module_param(nowayout, bool, 0);
  230. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
  231. MODULE_AUTHOR("John Crispin <john@phrozen.org>");
  232. MODULE_DESCRIPTION("Lantiq SoC Watchdog");
  233. MODULE_LICENSE("GPL");